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STC8Gx_REG.h
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1 /*-----------------------------------------------------------------------
2 | FILE DESCRIPTION |
3 -----------------------------------------------------------------------*/
4 /*----------------------------------------------------------------------
5  - File name : STC8Gx_REG.h
6  - Author : zeweni / slipperstree
7  - Update date : 2021.07.25
8  - Copyright(C) : 2020-2021 zeweni. All rights reserved.
9 -----------------------------------------------------------------------*/
10 /*------------------------------------------------------------------------
11 | COPYRIGHT NOTICE |
12 ------------------------------------------------------------------------*/
13 /*
14  * Copyright (C) 2021, zeweni (17870070675@163.com) / slipperstree (slipperstree@gmail.com)
15 
16  * This file is part of 8051 ELL low-layer libraries.
17 
18  * 8051 ELL low-layer libraries is free software: you can redistribute
19  * it and/or modify it under the terms of the Apache-2.0 License.
20 
21  * 8051 ELL low-layer libraries is distributed in the hope that it will
22  * be useful,but WITHOUT ANY WARRANTY; without even the implied warranty
23  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24  * Apache-2.0 License License for more details.
25 
26  * You should have received a copy of the Apache-2.0 License.8051 ELL
27  * low-layer libraries. If not, see <http://www.apache.org/licenses/>.
28 **/
29 /*-----------------------------------------------------------------------
30 | INCLUDES |
31 -----------------------------------------------------------------------*/
32 #ifndef __STC8Gx_REG_H_
33 #define __STC8Gx_REG_H_
34 
35 #include "ELL_TYPE.h"
36 
37 /*-----------------------------------------------------------------------
38 | REGISTER |
39 -----------------------------------------------------------------------*/
40 
41 /*--------------------------------------------------------
42 | @Description: kernel management |
43 --------------------------------------------------------*/
44 
45 //内核特殊功能寄存器
46 sfr ACC = 0xe0;
47 sfr B = 0xf0;
48 sfr PSW = 0xd0;
49 sbit CY = PSW^7;
50 sbit AC = PSW^6;
51 sbit F0 = PSW^5;
52 sbit RS1 = PSW^4;
53 sbit RS0 = PSW^3;
54 sbit OV = PSW^2;
55 sbit F1 = PSW^1;
56 sbit P = PSW^0;
57 sfr SP = 0x81;
58 sfr DPL = 0x82;
59 sfr DPH = 0x83;
60 sfr TA = 0xae;
61 sfr DPS = 0xe3;
62 sfr DPL1 = 0xe4;
63 sfr DPH1 = 0xe5;
64 
65 /*--------------------------------------------------------
66 | @Description: system management |
67 --------------------------------------------------------*/
68 
69 /* Base address define */
70 #define AUXR_ADDRESS 0x8EU
71 #define AUXR2_ADDRESS 0x8FU
72 #define PER_SW1_ADDRESS 0xA2U
73 #define PER_SW2_ADDRESS 0xBAU
74 
75 /* register */
76 sfr AUXR = AUXR_ADDRESS;
77 sfr AUXR2 = AUXR2_ADDRESS;
78 sfr P_SW1 = PER_SW1_ADDRESS;
79 sfr P_SW2 = PER_SW2_ADDRESS;
80 
81 #define EAXFR_ENABLE() P_SW2 |= 0x80
82 #define EAXFR_DISABLE() P_SW2 &= 0x7F
83 
84 /*--------------------------------------------------------
85 | @Description: System clock IO register structure |
86 --------------------------------------------------------*/
87 
88 typedef struct
89 {
90  __IO uint8_t CKSEL_REG; /*----Clock selection register */
91 
92  __IO uint8_t CLKDIV_REG; /*----Clock frequency division register */
93 
94  __IO uint8_t HIRCCR_REG; /*----High internal 24MHz oscillator control register */
95 
96  __IO uint8_t XOSCCR_REG; /*----External oscillator control register */
97 
98  __IO uint8_t IRC32KCR_REG; /*----Internal 32KHz oscillator control register */
99 
100  __IO uint8_t MCLKOCR_REG; /*----Master clock output control register */
101 
102 } SYSCLK_TypeDef;
103 
104 
105 /*--------------------------------------------------------
106 | @Description: System clock peripherals |
107 --------------------------------------------------------*/
108 
109 #define IRCBAND_ADDRESS 0x9DU
110 #define LIRTRIM_ADDRESS 0x9EU
111 #define IRTRIM_ADDRESS 0x9FU
112 
113 
114 /* System clock base address in the
115 internal expansion RAM area */
116 #define SYSCLK_BASE 0xFE00U
117 
118 #define CKSEL_ADDRESS (SYSCLK_BASE + 0x0000U)
119 #define CLKDIV_ADDRESS (SYSCLK_BASE + 0x0001U)
120 #define HIRCCR_ADDRESS (SYSCLK_BASE + 0x0002U)
121 #define XOSCCR_ADDRESS (SYSCLK_BASE + 0x0003U)
122 #define IRC32KCR_ADDRESS (SYSCLK_BASE + 0x0004U)
123 #define MCLKOCR_ADDRESS (SYSCLK_BASE + 0x0005U)
124 /* Define type of SYSCLK */
125 
126 #define SYSCLK (* (SYSCLK_TypeDef xdata *) SYSCLK_BASE)
127 
128 /* SYSCLIL register */
129 
130 #define CKSEL ( *(__IO uint8_t xdata *) CKSEL_ADDRESS)
131 #define CLKDIV ( *(__IO uint8_t xdata *) CLKDIV_ADDRESS)
132 #define IRC24MCR ( *(__IO uint8_t xdata *) HIRCCR_ADDRESS)
133 #define XOSCCR ( *(__IO uint8_t xdata *) XOSCCR_ADDRESS)
134 #define IRC32KCR ( *(__IO uint8_t xdata *) IRC32KCR_ADDRESS)
135 #define MCLKOCR ( *(__IO uint8_t xdata *) MCLKOCR_ADDRESS)
136 
137 /* IRC frequency adjustment register */
138 
139 sfr IRCBAND = IRCBAND_ADDRESS;
140 sfr IRTRIM = IRTRIM_ADDRESS;
141 sfr LIRTRIM = LIRTRIM_ADDRESS;
142 
143 #define IRC_22_1184M (*(__I uint8_t idata *)0xFA)
144 #define IRC_24M (*(__I uint8_t idata *)0xFB)
145 
146 /*--------------------------------------------------------
147 | @Description: Power peripherals |
148 --------------------------------------------------------*/
149 
150 /* Power base address */
151 #define PCON_ADDRESS 0x87U
152 #define VOCTRL_ADDRESS 0xBBU
153 
154 /* Power register */
155 sfr PCON = PCON_ADDRESS;
156 sfr VOCTRL = VOCTRL_ADDRESS;
157 
158 /*--------------------------------------------------------
159 | @Description: ISR peripherals |
160 --------------------------------------------------------*/
161 
162 /* ISR base address */
163 #define IE_ADDRESS 0xA8U
164 #define IE2_ADDRESS 0xAFU
165 #define IP_ADDRESS 0xB8U
166 #define IPH_ADDRESS 0xB7U
167 #define IP2_ADDRESS 0xB5U
168 #define IP2H_ADDRESS 0xB6U
169 #define IP3_ADDRESS 0xDFU
170 #define IP3H_ADDRESS 0xEEU
171 #define INTCLKO_ADDRESS 0x8FU
172 #define AUXINTIF_ADDRESS 0xEFU
173 #define INTE_GPIO_ADDRESS 0xFD00U
174 #define INTF_GPIO_ADDRESS 0xFD10U
175 
176 /* GPIO */
177 
178 #define P0INTE_ADDRESS INTE_GPIO_ADDRESS
179 #define P1INTE_ADDRESS (INTE_GPIO_ADDRESS + 0x0001U)
180 #define P2INTE_ADDRESS (INTE_GPIO_ADDRESS + 0x0002U)
181 #define P3INTE_ADDRESS (INTE_GPIO_ADDRESS + 0x0003U)
182 #define P4INTE_ADDRESS (INTE_GPIO_ADDRESS + 0x0004U)
183 #define P5INTE_ADDRESS (INTE_GPIO_ADDRESS + 0x0005U)
184 #define P6INTE_ADDRESS (INTE_GPIO_ADDRESS + 0x0006U)
185 #define P7INTE_ADDRESS (INTE_GPIO_ADDRESS + 0x0007U)
186 
187 #define P0INTF_ADDRESS INTF_GPIO_ADDRESS
188 #define P1INTF_ADDRESS (INTF_GPIO_ADDRESS + 0x0001U)
189 #define P2INTF_ADDRESS (INTF_GPIO_ADDRESS + 0x0002U)
190 #define P3INTF_ADDRESS (INTF_GPIO_ADDRESS + 0x0003U)
191 #define P4INTF_ADDRESS (INTF_GPIO_ADDRESS + 0x0004U)
192 #define P5INTF_ADDRESS (INTF_GPIO_ADDRESS + 0x0005U)
193 #define P6INTF_ADDRESS (INTF_GPIO_ADDRESS + 0x0006U)
194 #define P7INTF_ADDRESS (INTF_GPIO_ADDRESS + 0x0007U)
195 
196 /* ISR register */
197 sfr IE = IE_ADDRESS;
198 sfr IE2 = IE2_ADDRESS;
199 sfr IP = IP_ADDRESS;
200 sfr IPH = IPH_ADDRESS;
201 sfr IP2 = IP2H_ADDRESS;
202 sfr IP2H = IP2H_ADDRESS;
203 sfr IP3 = IP3_ADDRESS;
204 sfr IP3H = IP3H_ADDRESS;
205 sfr INTCLKO = INTCLKO_ADDRESS;
206 sfr AUXINTIF = AUXINTIF_ADDRESS;
207 
208 sbit EA = IE^7;
209 sbit ELVD = IE^6;
210 sbit EADC = IE^5;
211 sbit ES = IE^4;
212 sbit ET1 = IE^3;
213 sbit EX1 = IE^2;
214 sbit ET0 = IE^1;
215 sbit EX0 = IE^0;
216 
217 sbit PPCA = IP^7;
218 sbit PLVD = IP^6;
219 sbit PADC = IP^5;
220 sbit PS = IP^4;
221 sbit PT1 = IP^3;
222 sbit PX1 = IP^2;
223 sbit PT0 = IP^1;
224 sbit PX0 = IP^0;
225 
226 #define P0INTE ( *(__IO uint8_t xdata *) P0INTE_ADDRESS)
227 #define P1INTE ( *(__IO uint8_t xdata *) P1INTE_ADDRESS)
228 #define P2INTE ( *(__IO uint8_t xdata *) P2INTE_ADDRESS)
229 #define P3INTE ( *(__IO uint8_t xdata *) P3INTE_ADDRESS)
230 #define P4INTE ( *(__IO uint8_t xdata *) P4INTE_ADDRESS)
231 #define P5INTE ( *(__IO uint8_t xdata *) P5INTE_ADDRESS)
232 
233 #define P0INTF ( *(__IO uint8_t xdata *) P0INTF_ADDRESS)
234 #define P1INTF ( *(__IO uint8_t xdata *) P1INTF_ADDRESS)
235 #define P2INTF ( *(__IO uint8_t xdata *) P2INTF_ADDRESS)
236 #define P3INTF ( *(__IO uint8_t xdata *) P3INTF_ADDRESS)
237 #define P4INTF ( *(__IO uint8_t xdata *) P4INTF_ADDRESS)
238 #define P5INTF ( *(__IO uint8_t xdata *) P5INTF_ADDRESS)
239 
240 /*--------------------------------------------------------
241 | @Description: GPIO peripherals |
242 --------------------------------------------------------*/
243 
244 
245 /* Base address define */
246 #define GPIO_BASE 0x80U
247 #define PxM1_BASE 0x93U
248 #define PxM0_BASE 0x94U
249 #define BUS_SPEED_ADDRESS 0xA1U
250 
251 /* There are internal extended
252 ram areas below */
253 #define PxPU_BASE 0xFE10U
254 #define PxNCS_BASE 0xFE18U
255 #define PxSR_BASE 0xFE20U
256 #define PxDR_BASE 0xFE28U
257 #define PxIE_BASE 0xFE30U
258 
259 /* GPIO address define */
260 #define P0_ADDRESS GPIO_BASE
261 #define P1_ADDRESS 0x90U
262 #define P2_ADDRESS 0xA0U
263 #define P3_ADDRESS 0xB0U
264 #define P4_ADDRESS 0xC0U
265 #define P5_ADDRESS 0xC8U
266 #define P6_ADDRESS 0xE8U
267 #define P7_ADDRESS 0xF8U
268 
269 /*PxMx address define*/
270 #define P0M1_ADDRESS PxM1_BASE
271 #define P1M1_ADDRESS 0x91U
272 #define P2M1_ADDRESS 0x95U
273 #define P3M1_ADDRESS 0xB1U
274 #define P4M1_ADDRESS 0xB3U
275 #define P5M1_ADDRESS 0xC9U
276 #define P6M1_ADDRESS 0xCBU
277 #define P7M1_ADDRESS 0xE1U
278 
279 #define P0M0_ADDRESS PxM0_BASE
280 #define P1M0_ADDRESS 0x92U
281 #define P2M0_ADDRESS 0x96U
282 #define P3M0_ADDRESS 0xB2U
283 #define P4M0_ADDRESS 0xB4U
284 #define P5M0_ADDRESS 0xCAU
285 #define P6M0_ADDRESS 0xCCU
286 #define P7M0_ADDRESS 0xE2U
287 
288 /*GPIO pull up address */
289 #define P0PU_ADDRESS (PxPU_BASE + 0x00U)
290 #define P1PU_ADDRESS (PxPU_BASE + 0x01U)
291 #define P2PU_ADDRESS (PxPU_BASE + 0x02U)
292 #define P3PU_ADDRESS (PxPU_BASE + 0x03U)
293 #define P4PU_ADDRESS (PxPU_BASE + 0x04U)
294 #define P5PU_ADDRESS (PxPU_BASE + 0x05U)
295 #define P6PU_ADDRESS (PxPU_BASE + 0x06U)
296 #define P7PU_ADDRESS (PxPU_BASE + 0x07U)
297 
298 /*GPIO schmidt trigger address */
299 
300 #define P0NCS_ADDRESS (PxNCS_BASE + 0x00U)
301 #define P1NCS_ADDRESS (PxNCS_BASE + 0x01U)
302 #define P2NCS_ADDRESS (PxNCS_BASE + 0x02U)
303 #define P3NCS_ADDRESS (PxNCS_BASE + 0x03U)
304 #define P4NCS_ADDRESS (PxNCS_BASE + 0x04U)
305 #define P5NCS_ADDRESS (PxNCS_BASE + 0x05U)
306 #define P6NCS_ADDRESS (PxNCS_BASE + 0x06U)
307 #define P7NCS_ADDRESS (PxNCS_BASE + 0x07U)
308 
309 /* GPIO level conversion address */
310 
311 #define P0SR_ADDRESS (PxSR_BASE + 0x00U)
312 #define P1SR_ADDRESS (PxSR_BASE + 0x01U)
313 #define P2SR_ADDRESS (PxSR_BASE + 0x02U)
314 #define P3SR_ADDRESS (PxSR_BASE + 0x03U)
315 #define P4SR_ADDRESS (PxSR_BASE + 0x04U)
316 #define P5SR_ADDRESS (PxSR_BASE + 0x05U)
317 #define P6SR_ADDRESS (PxSR_BASE + 0x06U)
318 #define P7SR_ADDRESS (PxSR_BASE + 0x07U)
319 
320 /* GPIO drive current address */
321 
322 #define P0DR_ADDRESS (PxDR_BASE + 0x00U)
323 #define P1DR_ADDRESS (PxDR_BASE + 0x01U)
324 #define P2DR_ADDRESS (PxDR_BASE + 0x02U)
325 #define P3DR_ADDRESS (PxDR_BASE + 0x03U)
326 #define P4DR_ADDRESS (PxDR_BASE + 0x04U)
327 #define P5DR_ADDRESS (PxDR_BASE + 0x05U)
328 #define P6DR_ADDRESS (PxDR_BASE + 0x06U)
329 #define P7DR_ADDRESS (PxDR_BASE + 0x07U)
330 
331 /* GPIO intput enable address*/
332 #define P0IE_ADDRESS (PxIE_BASE + 0x00U)
333 #define P1IE_ADDRESS (PxIE_BASE + 0x01U)
334 #define P3IE_ADDRESS (PxIE_BASE + 0x03U)
335 
336 /* GPIO register */
337 sfr P0 = P0_ADDRESS;
338 sfr P1 = P1_ADDRESS;
339 sfr P2 = P2_ADDRESS;
340 sfr P3 = P3_ADDRESS;
341 sfr P4 = P4_ADDRESS;
342 sfr P5 = P5_ADDRESS;
343 sfr P6 = P6_ADDRESS;
344 sfr P7 = P7_ADDRESS;
345 
346 /* GPIO register */
347 sbit P00 = P0^0;
348 sbit P01 = P0^1;
349 sbit P02 = P0^2;
350 sbit P03 = P0^3;
351 sbit P04 = P0^4;
352 sbit P05 = P0^5;
353 sbit P06 = P0^6;
354 sbit P07 = P0^7;
355 
356 /* Pin register */
357 sbit P10 = P1^0;
358 sbit P11 = P1^1;
359 sbit P12 = P1^2;
360 sbit P13 = P1^3;
361 sbit P14 = P1^4;
362 sbit P15 = P1^5;
363 sbit P16 = P1^6;
364 sbit P17 = P1^7;
365 
366 sbit P20 = P2^0;
367 sbit P21 = P2^1;
368 sbit P22 = P2^2;
369 sbit P23 = P2^3;
370 sbit P24 = P2^4;
371 sbit P25 = P2^5;
372 sbit P26 = P2^6;
373 sbit P27 = P2^7;
374 
375 sbit P30 = P3^0;
376 sbit P31 = P3^1;
377 sbit P32 = P3^2;
378 sbit P33 = P3^3;
379 sbit P34 = P3^4;
380 sbit P35 = P3^5;
381 sbit P36 = P3^6;
382 sbit P37 = P3^7;
383 
384 sbit P40 = P4^0;
385 sbit P41 = P4^1;
386 sbit P42 = P4^2;
387 sbit P43 = P4^3;
388 sbit P44 = P4^4;
389 
390 sbit P50 = P5^0;
391 sbit P51 = P5^1;
392 sbit P52 = P5^2;
393 sbit P53 = P5^3;
394 sbit P54 = P5^4;
395 sbit P55 = P5^5;
396 sbit P56 = P5^6;
397 sbit P57 = P5^7;
398 
399 sbit P60 = P6^0;
400 sbit P61 = P6^1;
401 sbit P62 = P6^2;
402 sbit P63 = P6^3;
403 sbit P64 = P6^4;
404 sbit P65 = P6^5;
405 sbit P66 = P6^6;
406 sbit P67 = P6^7;
407 
408 sbit P70 = P7^0;
409 sbit P71 = P7^1;
410 sbit P72 = P7^2;
411 sbit P73 = P7^3;
412 sbit P74 = P7^4;
413 sbit P75 = P7^5;
414 sbit P76 = P7^6;
415 sbit P77 = P7^7;
416 
417 /* GPIO mode register */
418 sfr P0M1 = P0M1_ADDRESS;
419 sfr P1M1 = P1M1_ADDRESS;
420 sfr P2M1 = P2M1_ADDRESS;
421 sfr P3M1 = P3M1_ADDRESS;
422 sfr P4M1 = P4M1_ADDRESS;
423 sfr P5M1 = P5M1_ADDRESS;
424 sfr P6M1 = P6M1_ADDRESS;
425 sfr P7M1 = P7M1_ADDRESS;
426 
427 /* GPIO mode register */
428 sfr P0M0 = P0M0_ADDRESS;
429 sfr P1M0 = P1M0_ADDRESS;
430 sfr P2M0 = P2M0_ADDRESS;
431 sfr P3M0 = P3M0_ADDRESS;
432 sfr P4M0 = P4M0_ADDRESS;
433 sfr P5M0 = P5M0_ADDRESS;
434 sfr P6M0 = P6M0_ADDRESS;
435 sfr P7M0 = P7M0_ADDRESS;
436 
437 /* Bus speed control register */
438 sfr BUS_SPEED = BUS_SPEED_ADDRESS;
439 
440 /* GPIO Driver register */
441 
442 #define P0PU ( *(__IO uint8_t xdata *) P0PU_ADDRESS)
443 #define P1PU ( *(__IO uint8_t xdata *) P1PU_ADDRESS)
444 #define P2PU ( *(__IO uint8_t xdata *) P2PU_ADDRESS)
445 #define P3PU ( *(__IO uint8_t xdata *) P3PU_ADDRESS)
446 #define P4PU ( *(__IO uint8_t xdata *) P4PU_ADDRESS)
447 #define P5PU ( *(__IO uint8_t xdata *) P5PU_ADDRESS)
448 #define P6PU ( *(__IO uint8_t xdata *) P6PU_ADDRESS)
449 #define P7PU ( *(__IO uint8_t xdata *) P7PU_ADDRESS)
450 
451 #define P0SR ( *(__IO uint8_t xdata *) P0SR_ADDRESS)
452 #define P1SR ( *(__IO uint8_t xdata *) P1SR_ADDRESS)
453 #define P2SR ( *(__IO uint8_t xdata *) P2SR_ADDRESS)
454 #define P3SR ( *(__IO uint8_t xdata *) P3SR_ADDRESS)
455 #define P4SR ( *(__IO uint8_t xdata *) P4SR_ADDRESS)
456 #define P5SR ( *(__IO uint8_t xdata *) P5SR_ADDRESS)
457 #define P6SR ( *(__IO uint8_t xdata *) P6SR_ADDRESS)
458 #define P7SR ( *(__IO uint8_t xdata *) P7SR_ADDRESS)
459 
460 #define P0DR ( *(__IO uint8_t xdata *) P0DR_ADDRESS)
461 #define P1DR ( *(__IO uint8_t xdata *) P1DR_ADDRESS)
462 #define P2DR ( *(__IO uint8_t xdata *) P2DR_ADDRESS)
463 #define P3DR ( *(__IO uint8_t xdata *) P3DR_ADDRESS)
464 #define P4DR ( *(__IO uint8_t xdata *) P4DR_ADDRESS)
465 #define P5DR ( *(__IO uint8_t xdata *) P5DR_ADDRESS)
466 #define P6DR ( *(__IO uint8_t xdata *) P6DR_ADDRESS)
467 #define P7DR ( *(__IO uint8_t xdata *) P7DR_ADDRESS)
468 
469 #define P0IE ( *(__IO uint8_t xdata *) P0IE_ADDRESS)
470 #define P1IE ( *(__IO uint8_t xdata *) P1IE_ADDRESS)
471 #define P3IE ( *(__IO uint8_t xdata *) P3IE_ADDRESS)
472 //#define P2IE ( *(__IO uint8_t xdata *) P2IE_ADDRESS)
473 //#define P4IE ( *(__IO uint8_t xdata *) P4IE_ADDRESS)
474 //#define P5IE ( *(__IO uint8_t xdata *) P5IE_ADDRESS)
475 //#define P6IE ( *(__IO uint8_t xdata *) P6IE_ADDRESS)
476 //#define P7IE ( *(__IO uint8_t xdata *) P7IE_ADDRESS)
477 
478 #define P0NCS ( *(__IO uint8_t xdata *) P0NCS_ADDRESS)
479 #define P1NCS ( *(__IO uint8_t xdata *) P1NCS_ADDRESS)
480 #define P2NCS ( *(__IO uint8_t xdata *) P2NCS_ADDRESS)
481 #define P3NCS ( *(__IO uint8_t xdata *) P3NCS_ADDRESS)
482 #define P4NCS ( *(__IO uint8_t xdata *) P4NCS_ADDRESS)
483 #define P5NCS ( *(__IO uint8_t xdata *) P5NCS_ADDRESS)
484 #define P6NCS ( *(__IO uint8_t xdata *) P6NCS_ADDRESS)
485 #define P7NCS ( *(__IO uint8_t xdata *) P7NCS_ADDRESS)
486 
487 #define GPIO_Px(x) (P##x)
488 #define Px_M1(x) (P##x##M1) // GPIO_P0M1 GPIO_P0M0
489 #define Px_M0(x) (P##x##M0) // P0M1 P0M0
490 #define Px_PU(x) (P##x##PU)
491 #define Px_SR(x) (P##x##SR)
492 #define Px_DR(x) (P##x##DR)
493 #define Px_IE(x) (P##x##IE)
494 #define Px_NCS(x) (P##x##NCS)
495 
496 /*--------------------------------------------------------
497 | @Description: WDT peripherals |
498 --------------------------------------------------------*/
499 
500 /* Base address define */
501 
502 #define WDT_ADDRESS 0xC1U
503 #define RSTCFG_ADDRESS 0xFFU
504 
505 /* WDT register */
506 sfr WDT_CONTR = WDT_ADDRESS;
507 //sfr IAP_CONTR = IAR_ADDRESS;
508 sfr RSTCFG = RSTCFG_ADDRESS;
509 
510 /*--------------------------------------------------------
511 | @Description: TIMER peripherals |
512 --------------------------------------------------------*/
513 
514 /* Base address define */
515 #define TCON_ADDRESS 0x88U
516 #define TMOD_ADDRESS 0x89U
517 #define T0L_ADDRESS 0x8AU
518 #define T1L_ADDRESS 0x8BU
519 #define T0H_ADDRESS 0x8CU
520 #define T1H_ADDRESS 0x8DU
521 #define T4T3M_ADDRESS 0xD1U
522 #define T4H_ADDRESS 0xD2U
523 #define T4L_ADDRESS 0xD3U
524 #define T3H_ADDRESS 0xD4U
525 #define T3L_ADDRESS 0xD5U
526 #define T2H_ADDRESS 0xD6U
527 #define T2L_ADDRESS 0xD7U
528 #define WKTCL_ADDRESS 0xAAU
529 #define WKTCH_ADDRESS 0xABU
530 
531 #define TM2PS_ADDRESS 0xFEA2U
532 #define TM3PS_ADDRESS 0xFEA3U
533 #define TM4PS_ADDRESS 0xFEA4U
534 
535 /* TMOD */
536 #define T1_GATE 0x80
537 #define T1_CT 0x40
538 #define T1_M1 0x20
539 #define T1_M0 0x10
540 #define T0_GATE 0x08
541 #define T0_CT 0x04
542 #define T0_M1 0x02
543 #define T0_M0 0x01
544 
545 /* T4T3 */
546 #define T4R 0x80
547 #define T4_CT 0x40
548 #define T4x12 0x20
549 #define T4CLKO 0x10
550 #define T3R 0x08
551 #define T3_CT 0x04
552 #define T3x12 0x02
553 #define T3CLKO 0x01
554 
555 /* WKTCH */
556 #define WKTEN 0x80
557 
558 /* WDT_CONTR */
559 #define WDT_FLAG 0x80
560 #define EN_WDT 0x20
561 #define CLR_WDT 0x10
562 #define IDL_WDT 0x08
563 
564 /* TIMER register */
565 sfr TCON = TCON_ADDRESS;
566 sfr TMOD = TMOD_ADDRESS;
567 sfr T0L = T0L_ADDRESS;
568 sfr T1L = T1L_ADDRESS;
569 sfr T0H = T0H_ADDRESS;
570 sfr T1H = T1H_ADDRESS;
571 sfr TL0 = T0L_ADDRESS;
572 sfr TL1 = T1L_ADDRESS;
573 sfr TH0 = T0H_ADDRESS;
574 sfr TH1 = T1H_ADDRESS;
575 sfr T4T3M = T4T3M_ADDRESS;
576 sfr T4H = T4H_ADDRESS;
577 sfr T4L = T4L_ADDRESS;
578 sfr T3H = T3H_ADDRESS;
579 sfr T3L = T3L_ADDRESS;
580 sfr T2H = T2H_ADDRESS;
581 sfr T2L = T2L_ADDRESS;
582 sfr WKTCL = WKTCL_ADDRESS;
583 sfr WKTCH = WKTCH_ADDRESS;
584 
585 sbit TF1 = TCON^7;
586 sbit TR1 = TCON^6;
587 sbit TF0 = TCON^5;
588 sbit TR0 = TCON^4;
589 sbit IE1 = TCON^3;
590 sbit IE0 = TCON^1;
591 
592 #define TM2PS (*(__IO uint8_t xdata *)TM2PS_ADDRESS)
593 #define TM3PS (*(__IO uint8_t xdata *)TM3PS_ADDRESS)
594 #define TM4PS (*(__IO uint8_t xdata *)TM4PS_ADDRESS)
595 
596 /* Clock frequency address of timer5 */
597 
598 #define FWTH (*(__I uint8_t idata *)0xF8)
599 #define FWTL (*(__I uint8_t idata *)0xF9)
600 
601 /*--------------------------------------------------------
602 | @Description: EXTI peripherals |
603 --------------------------------------------------------*/
604 
605 /* EXTI register */
606 sbit IT0 = TCON^0;
607 sbit IT1 = TCON^2;
608 
609 /*--------------------------------------------------------
610 | @Description: UART peripherals |
611 --------------------------------------------------------*/
612 
613 /* Base address define */
614 
615 #define SCON_ADDRESS 0x98U
616 #define SBUF_ADDRESS 0x99U
617 #define S2CON_ADDRESS 0x9AU
618 #define S2BUF_ADDRESS 0x9BU
619 #define S3CON_ADDRESS 0xACU
620 #define S3BUF_ADDRESS 0xADU
621 #define S4CON_ADDRESS 0x84U
622 #define S4BUF_ADDRESS 0x85U
623 #define SADDR_ADDRESS 0xA9U
624 #define SADEN_ADDRESS 0xB9U
625 
626 /* S2CON */
627 #define S2SM0 0x80
628 #define S2ST4 0x40
629 #define S2SM2 0x20
630 #define S2REN 0x10
631 #define S2TB8 0x08
632 #define S2RB8 0x04
633 #define S2TI 0x02
634 #define S2RI 0x01
635 
636 /* S3CON */
637 #define S3SM0 0x80
638 #define S3ST4 0x40
639 #define S3SM2 0x20
640 #define S3REN 0x10
641 #define S3TB8 0x08
642 #define S3RB8 0x04
643 #define S3TI 0x02
644 #define S3RI 0x01
645 
646 /* S4CON */
647 #define S4SM0 0x80
648 #define S4ST4 0x40
649 #define S4SM2 0x20
650 #define S4REN 0x10
651 #define S4TB8 0x08
652 #define S4RB8 0x04
653 #define S4TI 0x02
654 #define S4RI 0x01
655 
656 /* UART register */
657 
658 sfr SCON = SCON_ADDRESS;
659 sfr SBUF = SBUF_ADDRESS;
660 sfr S2CON = S2CON_ADDRESS;
661 sfr S2BUF = S2BUF_ADDRESS;
662 sfr S3CON = S3CON_ADDRESS;
663 sfr S3BUF = S3BUF_ADDRESS;
664 sfr S4CON = S4CON_ADDRESS;
665 sfr S4BUF = S4BUF_ADDRESS;
666 sfr SADDR = SADDR_ADDRESS;
667 sfr SADEN = SADEN_ADDRESS;
668 
669 sbit SM0 = SCON^7;
670 sbit SM1 = SCON^6;
671 sbit SM2 = SCON^5;
672 sbit REN = SCON^4;
673 sbit TB8 = SCON^3;
674 sbit RB8 = SCON^2;
675 sbit TI = SCON^1;
676 sbit RI = SCON^0;
677 
678 /*--------------------------------------------------------
679 | @Description: COMP peripherals |
680 --------------------------------------------------------*/
681 
682 /* Base address define */
683 #define CMPCR1_ADDRESS 0xE6U
684 #define CMPCR2_ADDRESS 0xE7U
685 
686 /* CMPCR1 */
687 #define CMPEN 0x80
688 #define CMPIF 0x40
689 #define PIE 0x20
690 #define NIE 0x10
691 #define PIS 0x08
692 #define NIS 0x04
693 #define CMPOE 0x02
694 #define CMPRES 0x01
695 
696 /* CMPAR2 */
697 #define INVCMPO 0x80
698 #define DISFLT 0x40
699 
700 /* COMP register */
701 sfr CMPCR1 = CMPCR1_ADDRESS;
702 sfr CMPCR2 = CMPCR2_ADDRESS;
703 
704 /*--------------------------------------------------------
705 | @Description: ADC peripherals |
706 --------------------------------------------------------*/
707 
708 /* Base address define */
709 #define ADC_CONTR_ADDRESS 0xBCU
710 #define ADC_RES_ADDRESS 0xBDU
711 #define ADC_RESH_ADDRESS 0xBDU
712 #define ADC_RESL_ADDRESS 0xBEU
713 #define ADCCFG_ADDRESS 0xDEU
714 #define ADCTIM_ADDRESS 0xFEA8U
715 /* ADC_CONTR */
716 #define ADC_POWER 0x80
717 #define ADC_START 0x40
718 #define ADC_FLAG 0x20
719 
720 /* ADCCFG */
721 #define ADC_RESFMT 0x20
722 
723 
724 /* ADC register */
725 sfr ADC_CONTR = ADC_CONTR_ADDRESS;
726 sfr ADC_RES = ADC_RESH_ADDRESS;
727 sfr ADC_RESL = ADC_RESL_ADDRESS;
728 sfr ADCCFG = ADCCFG_ADDRESS;
729 
730 #define ADCTIM (*(__IO uint8_t xdata *)ADCTIM_ADDRESS)
731 
732 /*--------------------------------------------------------
733 | @Description: EEPROM peripherals |
734 --------------------------------------------------------*/
735 
736 /* Base address define */
737 #define IAP_DATA_ADDRESS 0xC2U
738 #define IAP_ADDRH_ADDRESS 0xC3U
739 #define IAP_ADDRL_ADDRESS 0xC4U
740 #define IAP_CMD_ADDRESS 0xC5U
741 #define IAP_TRIG_ADDRESS 0xC6U
742 #define IAP_CONTR_ADDRESS 0xC7U
743 #define IAP_TPS_ADDRESS 0xF5U
744 
745 #define ISP_DATA_ADDRESS 0xC2U
746 #define ISP_ADDRH_ADDRESS 0xC3U
747 #define ISP_ADDRL_ADDRESS 0xC4U
748 #define ISP_CMD_ADDRESS 0xC5U
749 #define ISP_TRIG_ADDRESS 0xC6U
750 #define ISP_CONTR_ADDRESS 0xC7U
751 
752 /* IAP_CMD */
753 #define IAP_IDL 0x00
754 #define IAP_READ 0x01
755 #define IAP_WRITE 0x02
756 #define IAP_ERASE 0x03
757 
758 /* IAP_CONTR */
759 #define IAPEN 0x80
760 #define SWBS 0x40
761 #define SWRST 0x20
762 #define CMD_FAIL 0x10
763 
764 /* EEPROM register */
765 sfr IAP_DATA = IAP_DATA_ADDRESS;
766 sfr IAP_ADDRH = IAP_ADDRH_ADDRESS;
767 sfr IAP_ADDRL = IAP_ADDRL_ADDRESS;
768 sfr IAP_CMD = IAP_CMD_ADDRESS;
769 sfr IAP_TRIG = IAP_TRIG_ADDRESS;
770 sfr IAP_CONTR = IAP_CONTR_ADDRESS;
771 sfr IAP_TPS = IAP_TPS_ADDRESS;
772 
773 sfr ISP_DATA = ISP_DATA_ADDRESS;
774 sfr ISP_ADDRH = ISP_ADDRH_ADDRESS;
775 sfr ISP_ADDRL = ISP_ADDRL_ADDRESS;
776 sfr ISP_CMD = ISP_CMD_ADDRESS;
777 sfr ISP_TRIG = ISP_TRIG_ADDRESS;
778 sfr ISP_CONTR = ISP_CONTR_ADDRESS;
779 
780 /*--------------------------------------------------------
781 | @Description: PCA peripherals |
782 --------------------------------------------------------*/
783 
784 /* Base address define */
785 #define CCON_ADDRESS 0xD8U
786 #define CMOD_ADDRESS 0xD9U
787 #define CL_ADDRESS 0xE9U
788 #define CH_ADDRESS 0xF9U
789 #define CCAPM0_ADDRESS 0xDAU
790 #define CCAPM1_ADDRESS 0xDBU
791 #define CCAPM2_ADDRESS 0xDCU
792 #define CCAP0L_ADDRESS 0xEAU
793 #define CCAP1L_ADDRESS 0xEBU
794 #define CCAP2L_ADDRESS 0xECU
795 #define CCAP0H_ADDRESS 0xFAU
796 #define CCAP1H_ADDRESS 0xFBU
797 #define CCAP2H_ADDRESS 0xFCU
798 #define PCA_PWM0_ADDRESS 0xF2U
799 #define PCA_PWM1_ADDRESS 0xF3U
800 #define PCA_PWM2_ADDRESS 0xF4U
801 
802 /* CMOD */
803 #define CIDL 0x80
804 #define ECF 0x01
805 
806 /* CCAPM0 */
807 #define ECOM0 0x40
808 #define CCAPP0 0x20
809 #define CCAPN0 0x10
810 #define MAT0 0x08
811 #define TOG0 0x04
812 #define PWM0 0x02
813 #define ECCF0 0x01
814 
815 /* CCAPM1 */
816 #define ECOM1 0x40
817 #define CCAPP1 0x20
818 #define CCAPN1 0x10
819 #define MAT1 0x08
820 #define TOG1 0x04
821 #define PWM1 0x02
822 #define ECCF1 0x01
823 
824 /* CCAMP2 */
825 #define ECOM2 0x40
826 #define CCAPP2 0x20
827 #define CCAPN2 0x10
828 #define MAT2 0x08
829 #define TOG2 0x04
830 #define PWM2 0x02
831 #define ECCF2 0x01
832 
833 /* PCA register */
834 sfr CCON = CCON_ADDRESS;
835 sfr CMOD = CMOD_ADDRESS;
836 sfr CL = CL_ADDRESS;
837 sfr CH = CH_ADDRESS;
838 sfr CCAPM0 = CCAPM0_ADDRESS;
839 sfr CCAPM1 = CCAPM1_ADDRESS;
840 sfr CCAPM2 = CCAPM2_ADDRESS;
841 sfr CCAP0L = CCAP0L_ADDRESS;
842 sfr CCAP1L = CCAP1L_ADDRESS;
843 sfr CCAP2L = CCAP2L_ADDRESS;
844 
845 sfr CCAP0H = CCAP0H_ADDRESS;
846 sfr CCAP1H = CCAP1H_ADDRESS;
847 sfr CCAP2H = CCAP2H_ADDRESS;
848 sfr PCA_PWM0 = PCA_PWM0_ADDRESS;
849 sfr PCA_PWM1 = PCA_PWM1_ADDRESS;
850 sfr PCA_PWM2 = PCA_PWM2_ADDRESS;
851 
852 sbit CF = CCON ^ 7;
853 sbit CR = CCON ^ 6;
854 sbit CCF3 = CCON ^ 3;
855 sbit CCF2 = CCON ^ 2;
856 sbit CCF1 = CCON ^ 1;
857 sbit CCF0 = CCON ^ 0;
858 
859 /*--------------------------------------------------------
860 | @Description: PWM peripherals |
861 --------------------------------------------------------*/
862 
863 /* Base address define */
864 #define PWMSET_ADDRESS 0xF1U
865 #define PWMCFG01_ADDRESS 0xF6U
866 #define PWMCFG23_ADDRESS 0xF7U
867 #define PWMCFG45_ADDRESS 0xFEU
868 
869 /* PWM0 control address define */
870 #define PWM0_BASE 0xFF00U
871 #define PWM0C_ADDRESS (PWM0_BASE + 0x00U)
872 #define PWM0CH_ADDRESS (PWM0C_ADDRESS + 0x00U)
873 #define PWM0CL_ADDRESS (PWM0CH_ADDRESS + 0x01U)
874 #define PWM0CKS_ADDRESS (PWM0CL_ADDRESS + 0x01U)
875 #define PWM0TADC_ADDRESS (PWM0CKS_ADDRESS + 0x01U)
876 #define PWM0TADCH_ADDRESS (PWM0TADC_ADDRESS + 0x00U)
877 #define PWM0TADCL_ADDRESS (PWM0TADCH_ADDRESS + 0x01U)
878 #define PWM0IF_ADDRESS (PWM0TADCL_ADDRESS + 0x01U)
879 #define PWM0FDCR_ADDRESS (PWM0IF_ADDRESS + 0x01U)
880 
881 /* PWM0.0-PWM0.7 channal address define */
882 #define PWM00T1_ADDRESS (PWM0FDCR_ADDRESS + 0x03U)
883 #define PWM00T1H_ADDRESS (PWM00T1_ADDRESS + 0x00U)
884 #define PWM00T1L_ADDRESS (PWM00T1H_ADDRESS + 0x01U)
885 #define PWM00T2_ADDRESS (PWM00T1L_ADDRESS + 0x01U)
886 #define PWM00T2H_ADDRESS (PWM00T2_ADDRESS + 0x00U)
887 #define PWM00T2L_ADDRESS (PWM00T2H_ADDRESS + 0x01U)
888 #define PWM00CR_ADDRESS (PWM00T2L_ADDRESS + 0x01U)
889 #define PWM00HLD_ADDRESS (PWM00CR_ADDRESS + 0x01U)
890 #define PWM01T1_ADDRESS (PWM00HLD_ADDRESS + 0x03U)
891 #define PWM01T1H_ADDRESS (PWM01T1_ADDRESS + 0x00U)
892 #define PWM01T1L_ADDRESS (PWM01T1H_ADDRESS + 0x01U)
893 #define PWM01T2_ADDRESS (PWM01T1L_ADDRESS + 0x01U)
894 #define PWM01T2H_ADDRESS (PWM01T2_ADDRESS + 0x00U)
895 #define PWM01T2L_ADDRESS (PWM01T2H_ADDRESS + 0x01U)
896 #define PWM01CR_ADDRESS (PWM01T2L_ADDRESS + 0x01U)
897 #define PWM01HLD_ADDRESS (PWM01CR_ADDRESS + 0x01U)
898 #define PWM02T1_ADDRESS (PWM01HLD_ADDRESS + 0x03U)
899 #define PWM02T1H_ADDRESS (PWM02T1_ADDRESS + 0x00U)
900 #define PWM02T1L_ADDRESS (PWM02T1H_ADDRESS + 0x01U)
901 #define PWM02T2_ADDRESS (PWM02T1L_ADDRESS + 0x01U)
902 #define PWM02T2H_ADDRESS (PWM02T2_ADDRESS + 0x00U)
903 #define PWM02T2L_ADDRESS (PWM02T2H_ADDRESS + 0x01U)
904 #define PWM02CR_ADDRESS (PWM02T2L_ADDRESS + 0x01U)
905 #define PWM02HLD_ADDRESS (PWM02CR_ADDRESS + 0x01U)
906 #define PWM03T1_ADDRESS (PWM02HLD_ADDRESS + 0x03U)
907 #define PWM03T1H_ADDRESS (PWM03T1_ADDRESS + 0x00U)
908 #define PWM03T1L_ADDRESS (PWM03T1H_ADDRESS + 0x01U)
909 #define PWM03T2_ADDRESS (PWM03T1L_ADDRESS + 0x01U)
910 #define PWM03T2H_ADDRESS (PWM03T2_ADDRESS + 0x00U)
911 #define PWM03T2L_ADDRESS (PWM03T2H_ADDRESS + 0x01U)
912 #define PWM03CR_ADDRESS (PWM03T2L_ADDRESS + 0x01U)
913 #define PWM03HLD_ADDRESS (PWM03CR_ADDRESS + 0x01U)
914 #define PWM04T1_ADDRESS (PWM03HLD_ADDRESS + 0x03U)
915 #define PWM04T1H_ADDRESS (PWM04T1_ADDRESS + 0x00U)
916 #define PWM04T1L_ADDRESS (PWM04T1H_ADDRESS + 0x01U)
917 #define PWM04T2_ADDRESS (PWM04T1L_ADDRESS + 0x01U)
918 #define PWM04T2H_ADDRESS (PWM04T2_ADDRESS + 0x00U)
919 #define PWM04T2L_ADDRESS (PWM04T2H_ADDRESS + 0x01U)
920 #define PWM04CR_ADDRESS (PWM04T2L_ADDRESS + 0x01U)
921 #define PWM04HLD_ADDRESS (PWM04CR_ADDRESS + 0x01U)
922 #define PWM05T1_ADDRESS (PWM04HLD_ADDRESS + 0x03U)
923 #define PWM05T1H_ADDRESS (PWM05T1_ADDRESS + 0x00U)
924 #define PWM05T1L_ADDRESS (PWM05T1H_ADDRESS + 0x01U)
925 #define PWM05T2_ADDRESS (PWM05T1L_ADDRESS + 0x01U)
926 #define PWM05T2H_ADDRESS (PWM05T2_ADDRESS + 0x00U)
927 #define PWM05T2L_ADDRESS (PWM05T2H_ADDRESS + 0x01U)
928 #define PWM05CR_ADDRESS (PWM05T2L_ADDRESS + 0x01U)
929 #define PWM05HLD_ADDRESS (PWM05CR_ADDRESS + 0x01U)
930 #define PWM06T1_ADDRESS (PWM05HLD_ADDRESS + 0x03U)
931 #define PWM06T1H_ADDRESS (PWM06T1_ADDRESS + 0x00U)
932 #define PWM06T1L_ADDRESS (PWM06T1H_ADDRESS + 0x01U)
933 #define PWM06T2_ADDRESS (PWM06T1L_ADDRESS + 0x01U)
934 #define PWM06T2H_ADDRESS (PWM06T2_ADDRESS + 0x00U)
935 #define PWM06T2L_ADDRESS (PWM06T2H_ADDRESS + 0x01U)
936 #define PWM06CR_ADDRESS (PWM06T2L_ADDRESS + 0x01U)
937 #define PWM06HLD_ADDRESS (PWM06CR_ADDRESS + 0x01U)
938 #define PWM07T1_ADDRESS (PWM06HLD_ADDRESS + 0x03U)
939 #define PWM07T1H_ADDRESS (PWM07T1_ADDRESS + 0x00U)
940 #define PWM07T1L_ADDRESS (PWM07T1H_ADDRESS + 0x01U)
941 #define PWM07T2_ADDRESS (PWM07T1L_ADDRESS + 0x01U)
942 #define PWM07T2H_ADDRESS (PWM07T2_ADDRESS + 0x00U)
943 #define PWM07T2L_ADDRESS (PWM07T2H_ADDRESS + 0x01U)
944 #define PWM07CR_ADDRESS (PWM07T2L_ADDRESS + 0x01U)
945 #define PWM07HLD_ADDRESS (PWM07CR_ADDRESS + 0x01U)
946 
947 /* PWM1 control address define */
948 #define PWM1_BASE 0xFF50U
949 #define PWM1C_ADDRESS (PWM1_BASE + 0x00U)
950 #define PWM1CH_ADDRESS (PWM1C_ADDRESS + 0x00U)
951 #define PWM1CL_ADDRESS (PWM1CH_ADDRESS + 0x01U)
952 #define PWM1CKS_ADDRESS (PWM1CL_ADDRESS + 0x01U)
953 #define PWM1TADC_ADDRESS (PWM1CKS_ADDRESS + 0x01U)
954 #define PWM1TADCH_ADDRESS (PWM1TADC_ADDRESS + 0x00U)
955 #define PWM1TADCL_ADDRESS (PWM1TADCH_ADDRESS + 0x01U)
956 #define PWM1IF_ADDRESS (PWM1TADCL_ADDRESS + 0x01U)
957 #define PWM1FDCR_ADDRESS (PWM1IF_ADDRESS + 0x01U)
958 
959 /* PWM1.0-PWM1.7 channal address define */
960 #define PWM10T1_ADDRESS (PWM1FDCR_ADDRESS + 0x03U)
961 #define PWM10T1H_ADDRESS (PWM10T1_ADDRESS + 0x00U)
962 #define PWM10T1L_ADDRESS (PWM10T1H_ADDRESS + 0x01U)
963 #define PWM10T2_ADDRESS (PWM10T1L_ADDRESS + 0x01U)
964 #define PWM10T2H_ADDRESS (PWM10T2_ADDRESS + 0x00U)
965 #define PWM10T2L_ADDRESS (PWM10T2H_ADDRESS + 0x01U)
966 #define PWM10CR_ADDRESS (PWM10T2L_ADDRESS + 0x01U)
967 #define PWM10HLD_ADDRESS (PWM10CR_ADDRESS + 0x01U)
968 #define PWM11T1_ADDRESS (PWM10HLD_ADDRESS + 0x03U)
969 #define PWM11T1H_ADDRESS (PWM11T1_ADDRESS + 0x00U)
970 #define PWM11T1L_ADDRESS (PWM11T1H_ADDRESS + 0x01U)
971 #define PWM11T2_ADDRESS (PWM11T1L_ADDRESS + 0x01U)
972 #define PWM11T2H_ADDRESS (PWM11T2_ADDRESS + 0x00U)
973 #define PWM11T2L_ADDRESS (PWM11T2H_ADDRESS + 0x01U)
974 #define PWM11CR_ADDRESS (PWM11T2L_ADDRESS + 0x01U)
975 #define PWM11HLD_ADDRESS (PWM11CR_ADDRESS + 0x01U)
976 #define PWM12T1_ADDRESS (PWM11HLD_ADDRESS + 0x03U)
977 #define PWM12T1H_ADDRESS (PWM12T1_ADDRESS + 0x00U)
978 #define PWM12T1L_ADDRESS (PWM12T1H_ADDRESS + 0x01U)
979 #define PWM12T2_ADDRESS (PWM12T1L_ADDRESS + 0x01U)
980 #define PWM12T2H_ADDRESS (PWM12T2_ADDRESS + 0x00U)
981 #define PWM12T2L_ADDRESS (PWM12T2H_ADDRESS + 0x01U)
982 #define PWM12CR_ADDRESS (PWM12T2L_ADDRESS + 0x01U)
983 #define PWM12HLD_ADDRESS (PWM12CR_ADDRESS + 0x01U)
984 #define PWM13T1_ADDRESS (PWM12HLD_ADDRESS + 0x03U)
985 #define PWM13T1H_ADDRESS (PWM13T1_ADDRESS + 0x00U)
986 #define PWM13T1L_ADDRESS (PWM13T1H_ADDRESS + 0x01U)
987 #define PWM13T2_ADDRESS (PWM13T1L_ADDRESS + 0x01U)
988 #define PWM13T2H_ADDRESS (PWM13T2_ADDRESS + 0x00U)
989 #define PWM13T2L_ADDRESS (PWM13T2H_ADDRESS + 0x01U)
990 #define PWM13CR_ADDRESS (PWM13T2L_ADDRESS + 0x01U)
991 #define PWM13HLD_ADDRESS (PWM13CR_ADDRESS + 0x01U)
992 #define PWM14T1_ADDRESS (PWM13HLD_ADDRESS + 0x03U)
993 #define PWM14T1H_ADDRESS (PWM14T1_ADDRESS + 0x00U)
994 #define PWM14T1L_ADDRESS (PWM14T1H_ADDRESS + 0x01U)
995 #define PWM14T2_ADDRESS (PWM14T1L_ADDRESS + 0x01U)
996 #define PWM14T2H_ADDRESS (PWM14T2_ADDRESS + 0x00U)
997 #define PWM14T2L_ADDRESS (PWM14T2H_ADDRESS + 0x01U)
998 #define PWM14CR_ADDRESS (PWM14T2L_ADDRESS + 0x01U)
999 #define PWM14HLD_ADDRESS (PWM14CR_ADDRESS + 0x01U)
1000 #define PWM15T1_ADDRESS (PWM14HLD_ADDRESS + 0x03U)
1001 #define PWM15T1H_ADDRESS (PWM15T1_ADDRESS + 0x00U)
1002 #define PWM15T1L_ADDRESS (PWM15T1H_ADDRESS + 0x01U)
1003 #define PWM15T2_ADDRESS (PWM15T1L_ADDRESS + 0x01U)
1004 #define PWM15T2H_ADDRESS (PWM15T2_ADDRESS + 0x00U)
1005 #define PWM15T2L_ADDRESS (PWM15T2H_ADDRESS + 0x01U)
1006 #define PWM15CR_ADDRESS (PWM15T2L_ADDRESS + 0x01U)
1007 #define PWM15HLD_ADDRESS (PWM15CR_ADDRESS + 0x01U)
1008 #define PWM16T1_ADDRESS (PWM15HLD_ADDRESS + 0x03U)
1009 #define PWM16T1H_ADDRESS (PWM16T1_ADDRESS + 0x00U)
1010 #define PWM16T1L_ADDRESS (PWM16T1H_ADDRESS + 0x01U)
1011 #define PWM16T2_ADDRESS (PWM16T1L_ADDRESS + 0x01U)
1012 #define PWM16T2H_ADDRESS (PWM16T2_ADDRESS + 0x00U)
1013 #define PWM16T2L_ADDRESS (PWM16T2H_ADDRESS + 0x01U)
1014 #define PWM16CR_ADDRESS (PWM16T2L_ADDRESS + 0x01U)
1015 #define PWM16HLD_ADDRESS (PWM16CR_ADDRESS + 0x01U)
1016 #define PWM17T1_ADDRESS (PWM16HLD_ADDRESS + 0x03U)
1017 #define PWM17T1H_ADDRESS (PWM17T1_ADDRESS + 0x00U)
1018 #define PWM17T1L_ADDRESS (PWM17T1H_ADDRESS + 0x01U)
1019 #define PWM17T2_ADDRESS (PWM17T1L_ADDRESS + 0x01U)
1020 #define PWM17T2H_ADDRESS (PWM17T2_ADDRESS + 0x00U)
1021 #define PWM17T2L_ADDRESS (PWM17T2H_ADDRESS + 0x01U)
1022 #define PWM17CR_ADDRESS (PWM17T2L_ADDRESS + 0x01U)
1023 #define PWM17HLD_ADDRESS (PWM17CR_ADDRESS + 0x01U)
1024 
1025 /* PWM2 control address define */
1026 #define PWM2_BASE 0xFFA0U
1027 #define PWM2C_ADDRESS (PWM2_BASE + 0x00U)
1028 #define PWM2CH_ADDRESS (PWM2C_ADDRESS + 0x00U)
1029 #define PWM2CL_ADDRESS (PWM2CH_ADDRESS + 0x01U)
1030 #define PWM2CKS_ADDRESS (PWM2CL_ADDRESS + 0x01U)
1031 #define PWM2TADC_ADDRESS (PWM2CKS_ADDRESS + 0x01U)
1032 #define PWM2TADCH_ADDRESS (PWM2TADC_ADDRESS + 0x00U)
1033 #define PWM2TADCL_ADDRESS (PWM2TADCH_ADDRESS + 0x01U)
1034 #define PWM2IF_ADDRESS (PWM2TADCL_ADDRESS + 0x01U)
1035 #define PWM2FDCR_ADDRESS (PWM2IF_ADDRESS + 0x01U)
1036 
1037 /* PWM2.0-PWM2.7 channal address define */
1038 #define PWM20T1_ADDRESS (PWM2FDCR_ADDRESS + 0x03U)
1039 #define PWM20T1H_ADDRESS (PWM20T1_ADDRESS + 0x00U)
1040 #define PWM20T1L_ADDRESS (PWM20T1H_ADDRESS + 0x01U)
1041 #define PWM20T2_ADDRESS (PWM20T1L_ADDRESS + 0x01U)
1042 #define PWM20T2H_ADDRESS (PWM20T2_ADDRESS + 0x00U)
1043 #define PWM20T2L_ADDRESS (PWM20T2H_ADDRESS + 0x01U)
1044 #define PWM20CR_ADDRESS (PWM20T2L_ADDRESS + 0x01U)
1045 #define PWM20HLD_ADDRESS (PWM20CR_ADDRESS + 0x01U)
1046 #define PWM21T1_ADDRESS (PWM20HLD_ADDRESS + 0x03U)
1047 #define PWM21T1H_ADDRESS (PWM21T1_ADDRESS + 0x00U)
1048 #define PWM21T1L_ADDRESS (PWM21T1H_ADDRESS + 0x01U)
1049 #define PWM21T2_ADDRESS (PWM21T1L_ADDRESS + 0x01U)
1050 #define PWM21T2H_ADDRESS (PWM21T2_ADDRESS + 0x00U)
1051 #define PWM21T2L_ADDRESS (PWM21T2H_ADDRESS + 0x01U)
1052 #define PWM21CR_ADDRESS (PWM21T2L_ADDRESS + 0x01U)
1053 #define PWM21HLD_ADDRESS (PWM21CR_ADDRESS + 0x01U)
1054 #define PWM22T1_ADDRESS (PWM21HLD_ADDRESS + 0x03U)
1055 #define PWM22T1H_ADDRESS (PWM22T1_ADDRESS + 0x00U)
1056 #define PWM22T1L_ADDRESS (PWM22T1H_ADDRESS + 0x01U)
1057 #define PWM22T2_ADDRESS (PWM22T1L_ADDRESS + 0x01U)
1058 #define PWM22T2H_ADDRESS (PWM22T2_ADDRESS + 0x00U)
1059 #define PWM22T2L_ADDRESS (PWM22T2H_ADDRESS + 0x01U)
1060 #define PWM22CR_ADDRESS (PWM22T2L_ADDRESS + 0x01U)
1061 #define PWM22HLD_ADDRESS (PWM22CR_ADDRESS + 0x01U)
1062 #define PWM23T1_ADDRESS (PWM22HLD_ADDRESS + 0x03U)
1063 #define PWM23T1H_ADDRESS (PWM23T1_ADDRESS + 0x00U)
1064 #define PWM23T1L_ADDRESS (PWM23T1H_ADDRESS + 0x01U)
1065 #define PWM23T2_ADDRESS (PWM23T1L_ADDRESS + 0x01U)
1066 #define PWM23T2H_ADDRESS (PWM23T2_ADDRESS + 0x00U)
1067 #define PWM23T2L_ADDRESS (PWM23T2H_ADDRESS + 0x01U)
1068 #define PWM23CR_ADDRESS (PWM23T2L_ADDRESS + 0x01U)
1069 #define PWM23HLD_ADDRESS (PWM23CR_ADDRESS + 0x01U)
1070 #define PWM24T1_ADDRESS (PWM23HLD_ADDRESS + 0x03U)
1071 #define PWM24T1H_ADDRESS (PWM24T1_ADDRESS + 0x00U)
1072 #define PWM24T1L_ADDRESS (PWM24T1H_ADDRESS + 0x01U)
1073 #define PWM24T2_ADDRESS (PWM24T1L_ADDRESS + 0x01U)
1074 #define PWM24T2H_ADDRESS (PWM24T2_ADDRESS + 0x00U)
1075 #define PWM24T2L_ADDRESS (PWM24T2H_ADDRESS + 0x01U)
1076 #define PWM24CR_ADDRESS (PWM24T2L_ADDRESS + 0x01U)
1077 #define PWM24HLD_ADDRESS (PWM24CR_ADDRESS + 0x01U)
1078 #define PWM25T1_ADDRESS (PWM24HLD_ADDRESS + 0x03U)
1079 #define PWM25T1H_ADDRESS (PWM25T1_ADDRESS + 0x00U)
1080 #define PWM25T1L_ADDRESS (PWM25T1H_ADDRESS + 0x01U)
1081 #define PWM25T2_ADDRESS (PWM25T1L_ADDRESS + 0x01U)
1082 #define PWM25T2H_ADDRESS (PWM25T2_ADDRESS + 0x00U)
1083 #define PWM25T2L_ADDRESS (PWM25T2H_ADDRESS + 0x01U)
1084 #define PWM25CR_ADDRESS (PWM25T2L_ADDRESS + 0x01U)
1085 #define PWM25HLD_ADDRESS (PWM25CR_ADDRESS + 0x01U)
1086 #define PWM26T1_ADDRESS (PWM25HLD_ADDRESS + 0x03U)
1087 #define PWM26T1H_ADDRESS (PWM26T1_ADDRESS + 0x00U)
1088 #define PWM26T1L_ADDRESS (PWM26T1H_ADDRESS + 0x01U)
1089 #define PWM26T2_ADDRESS (PWM26T1L_ADDRESS + 0x01U)
1090 #define PWM26T2H_ADDRESS (PWM26T2_ADDRESS + 0x00U)
1091 #define PWM26T2L_ADDRESS (PWM26T2H_ADDRESS + 0x01U)
1092 #define PWM26CR_ADDRESS (PWM26T2L_ADDRESS + 0x01U)
1093 #define PWM26HLD_ADDRESS (PWM26CR_ADDRESS + 0x01U)
1094 #define PWM27T1_ADDRESS (PWM26HLD_ADDRESS + 0x03U)
1095 #define PWM27T1H_ADDRESS (PWM27T1_ADDRESS + 0x00U)
1096 #define PWM27T1L_ADDRESS (PWM27T1H_ADDRESS + 0x01U)
1097 #define PWM27T2_ADDRESS (PWM27T1L_ADDRESS + 0x01U)
1098 #define PWM27T2H_ADDRESS (PWM27T2_ADDRESS + 0x00U)
1099 #define PWM27T2L_ADDRESS (PWM27T2H_ADDRESS + 0x01U)
1100 #define PWM27CR_ADDRESS (PWM27T2L_ADDRESS + 0x01U)
1101 #define PWM27HLD_ADDRESS (PWM27CR_ADDRESS + 0x01U)
1102 
1103 /* PWM3 control address define */
1104 #define PWM3_BASE 0xFC00U
1105 #define PWM3C_ADDRESS (PWM3_BASE + 0x00U)
1106 #define PWM3CH_ADDRESS (PWM3C_ADDRESS + 0x00U)
1107 #define PWM3CL_ADDRESS (PWM3CH_ADDRESS + 0x01U)
1108 #define PWM3CKS_ADDRESS (PWM3CL_ADDRESS + 0x01U)
1109 #define PWM3TADC_ADDRESS (PWM3CKS_ADDRESS + 0x01U)
1110 #define PWM3TADCH_ADDRESS (PWM3TADC_ADDRESS + 0x00U)
1111 #define PWM3TADCL_ADDRESS (PWM3TADCH_ADDRESS + 0x01U)
1112 #define PWM3IF_ADDRESS (PWM3TADCL_ADDRESS + 0x01U)
1113 #define PWM3FDCR_ADDRESS (PWM3IF_ADDRESS + 0x01U)
1114 
1115 /* PWM3.0-PWM3.7 channal address define */
1116 #define PWM30T1_ADDRESS (PWM3FDCR_ADDRESS + 0x03U)
1117 #define PWM30T1H_ADDRESS (PWM30T1_ADDRESS + 0x00U)
1118 #define PWM30T1L_ADDRESS (PWM30T1H_ADDRESS + 0x01U)
1119 #define PWM30T2_ADDRESS (PWM30T1L_ADDRESS + 0x01U)
1120 #define PWM30T2H_ADDRESS (PWM30T2_ADDRESS + 0x00U)
1121 #define PWM30T2L_ADDRESS (PWM30T2H_ADDRESS + 0x01U)
1122 #define PWM30CR_ADDRESS (PWM30T2L_ADDRESS + 0x01U)
1123 #define PWM30HLD_ADDRESS (PWM30CR_ADDRESS + 0x01U)
1124 #define PWM31T1_ADDRESS (PWM30HLD_ADDRESS + 0x03U)
1125 #define PWM31T1H_ADDRESS (PWM31T1_ADDRESS + 0x00U)
1126 #define PWM31T1L_ADDRESS (PWM31T1H_ADDRESS + 0x01U)
1127 #define PWM31T2_ADDRESS (PWM31T1L_ADDRESS + 0x01U)
1128 #define PWM31T2H_ADDRESS (PWM31T2_ADDRESS + 0x00U)
1129 #define PWM31T2L_ADDRESS (PWM31T2H_ADDRESS + 0x01U)
1130 #define PWM31CR_ADDRESS (PWM31T2L_ADDRESS + 0x01U)
1131 #define PWM31HLD_ADDRESS (PWM31CR_ADDRESS + 0x01U)
1132 #define PWM32T1_ADDRESS (PWM31HLD_ADDRESS + 0x03U)
1133 #define PWM32T1H_ADDRESS (PWM32T1_ADDRESS + 0x00U)
1134 #define PWM32T1L_ADDRESS (PWM32T1H_ADDRESS + 0x01U)
1135 #define PWM32T2_ADDRESS (PWM32T1L_ADDRESS + 0x01U)
1136 #define PWM32T2H_ADDRESS (PWM32T2_ADDRESS + 0x00U)
1137 #define PWM32T2L_ADDRESS (PWM32T2H_ADDRESS + 0x01U)
1138 #define PWM32CR_ADDRESS (PWM32T2L_ADDRESS + 0x01U)
1139 #define PWM32HLD_ADDRESS (PWM32CR_ADDRESS + 0x01U)
1140 #define PWM33T1_ADDRESS (PWM32HLD_ADDRESS + 0x03U)
1141 #define PWM33T1H_ADDRESS (PWM33T1_ADDRESS + 0x00U)
1142 #define PWM33T1L_ADDRESS (PWM33T1H_ADDRESS + 0x01U)
1143 #define PWM33T2_ADDRESS (PWM33T1L_ADDRESS + 0x01U)
1144 #define PWM33T2H_ADDRESS (PWM33T2_ADDRESS + 0x00U)
1145 #define PWM33T2L_ADDRESS (PWM33T2H_ADDRESS + 0x01U)
1146 #define PWM33CR_ADDRESS (PWM33T2L_ADDRESS + 0x01U)
1147 #define PWM33HLD_ADDRESS (PWM33CR_ADDRESS + 0x01U)
1148 #define PWM34T1_ADDRESS (PWM33HLD_ADDRESS + 0x03U)
1149 #define PWM34T1H_ADDRESS (PWM34T1_ADDRESS + 0x00U)
1150 #define PWM34T1L_ADDRESS (PWM34T1H_ADDRESS + 0x01U)
1151 #define PWM34T2_ADDRESS (PWM34T1L_ADDRESS + 0x01U)
1152 #define PWM34T2H_ADDRESS (PWM34T2_ADDRESS + 0x00U)
1153 #define PWM34T2L_ADDRESS (PWM34T2H_ADDRESS + 0x01U)
1154 #define PWM34CR_ADDRESS (PWM34T2L_ADDRESS + 0x01U)
1155 #define PWM34HLD_ADDRESS (PWM34CR_ADDRESS + 0x01U)
1156 #define PWM35T1_ADDRESS (PWM34HLD_ADDRESS + 0x03U)
1157 #define PWM35T1H_ADDRESS (PWM35T1_ADDRESS + 0x00U)
1158 #define PWM35T1L_ADDRESS (PWM35T1H_ADDRESS + 0x01U)
1159 #define PWM35T2_ADDRESS (PWM35T1L_ADDRESS + 0x01U)
1160 #define PWM35T2H_ADDRESS (PWM35T2_ADDRESS + 0x00U)
1161 #define PWM35T2L_ADDRESS (PWM35T2H_ADDRESS + 0x01U)
1162 #define PWM35CR_ADDRESS (PWM35T2L_ADDRESS + 0x01U)
1163 #define PWM35HLD_ADDRESS (PWM35CR_ADDRESS + 0x01U)
1164 #define PWM36T1_ADDRESS (PWM35HLD_ADDRESS + 0x03U)
1165 #define PWM36T1H_ADDRESS (PWM36T1_ADDRESS + 0x00U)
1166 #define PWM36T1L_ADDRESS (PWM36T1H_ADDRESS + 0x01U)
1167 #define PWM36T2_ADDRESS (PWM36T1L_ADDRESS + 0x01U)
1168 #define PWM36T2H_ADDRESS (PWM36T2_ADDRESS + 0x00U)
1169 #define PWM36T2L_ADDRESS (PWM36T2H_ADDRESS + 0x01U)
1170 #define PWM36CR_ADDRESS (PWM36T2L_ADDRESS + 0x01U)
1171 #define PWM36HLD_ADDRESS (PWM36CR_ADDRESS + 0x01U)
1172 #define PWM37T1_ADDRESS (PWM36HLD_ADDRESS + 0x03U)
1173 #define PWM37T1H_ADDRESS (PWM37T1_ADDRESS + 0x00U)
1174 #define PWM37T1L_ADDRESS (PWM37T1H_ADDRESS + 0x01U)
1175 #define PWM37T2_ADDRESS (PWM37T1L_ADDRESS + 0x01U)
1176 #define PWM37T2H_ADDRESS (PWM37T2_ADDRESS + 0x00U)
1177 #define PWM37T2L_ADDRESS (PWM37T2H_ADDRESS + 0x01U)
1178 #define PWM37CR_ADDRESS (PWM37T2L_ADDRESS + 0x01U)
1179 #define PWM37HLD_ADDRESS (PWM37CR_ADDRESS + 0x01U)
1180 
1181 /* PWM4 control address define */
1182 #define PWM4_BASE 0xFC50U
1183 #define PWM4C_ADDRESS (PWM4_BASE + 0x00U)
1184 #define PWM4CH_ADDRESS (PWM4C_ADDRESS + 0x00U)
1185 #define PWM4CL_ADDRESS (PWM4CH_ADDRESS + 0x01U)
1186 #define PWM4CKS_ADDRESS (PWM4CL_ADDRESS + 0x01U)
1187 #define PWM4TADC_ADDRESS (PWM4CKS_ADDRESS + 0x01U)
1188 #define PWM4TADCH_ADDRESS (PWM4TADC_ADDRESS + 0x00U)
1189 #define PWM4TADCL_ADDRESS (PWM4TADCH_ADDRESS + 0x01U)
1190 #define PWM4IF_ADDRESS (PWM4TADCL_ADDRESS + 0x01U)
1191 #define PWM4FDCR_ADDRESS (PWM4IF_ADDRESS + 0x01U)
1192 
1193 /* PWM4.0-PWM4.7 channal address define */
1194 #define PWM40T1_ADDRESS (PWM4FDCR_ADDRESS + 0x03U)
1195 #define PWM40T1H_ADDRESS (PWM40T1_ADDRESS + 0x00U)
1196 #define PWM40T1L_ADDRESS (PWM40T1H_ADDRESS + 0x01U)
1197 #define PWM40T2_ADDRESS (PWM40T1L_ADDRESS + 0x01U)
1198 #define PWM40T2H_ADDRESS (PWM40T2_ADDRESS + 0x00U)
1199 #define PWM40T2L_ADDRESS (PWM40T2H_ADDRESS + 0x01U)
1200 #define PWM40CR_ADDRESS (PWM40T2L_ADDRESS + 0x01U)
1201 #define PWM40HLD_ADDRESS (PWM40CR_ADDRESS + 0x01U)
1202 #define PWM41T1_ADDRESS (PWM40HLD_ADDRESS + 0x03U)
1203 #define PWM41T1H_ADDRESS (PWM41T1_ADDRESS + 0x00U)
1204 #define PWM41T1L_ADDRESS (PWM41T1H_ADDRESS + 0x01U)
1205 #define PWM41T2_ADDRESS (PWM41T1L_ADDRESS + 0x01U)
1206 #define PWM41T2H_ADDRESS (PWM41T2_ADDRESS + 0x00U)
1207 #define PWM41T2L_ADDRESS (PWM41T2H_ADDRESS + 0x01U)
1208 #define PWM41CR_ADDRESS (PWM41T2L_ADDRESS + 0x01U)
1209 #define PWM41HLD_ADDRESS (PWM41CR_ADDRESS + 0x01U)
1210 #define PWM42T1_ADDRESS (PWM41HLD_ADDRESS + 0x03U)
1211 #define PWM42T1H_ADDRESS (PWM42T1_ADDRESS + 0x00U)
1212 #define PWM42T1L_ADDRESS (PWM42T1H_ADDRESS + 0x01U)
1213 #define PWM42T2_ADDRESS (PWM42T1L_ADDRESS + 0x01U)
1214 #define PWM42T2H_ADDRESS (PWM42T2_ADDRESS + 0x00U)
1215 #define PWM42T2L_ADDRESS (PWM42T2H_ADDRESS + 0x01U)
1216 #define PWM42CR_ADDRESS (PWM42T2L_ADDRESS + 0x01U)
1217 #define PWM42HLD_ADDRESS (PWM42CR_ADDRESS + 0x01U)
1218 #define PWM43T1_ADDRESS (PWM42HLD_ADDRESS + 0x03U)
1219 #define PWM43T1H_ADDRESS (PWM43T1_ADDRESS + 0x00U)
1220 #define PWM43T1L_ADDRESS (PWM43T1H_ADDRESS + 0x01U)
1221 #define PWM43T2_ADDRESS (PWM43T1L_ADDRESS + 0x01U)
1222 #define PWM43T2H_ADDRESS (PWM43T2_ADDRESS + 0x00U)
1223 #define PWM43T2L_ADDRESS (PWM43T2H_ADDRESS + 0x01U)
1224 #define PWM43CR_ADDRESS (PWM43T2L_ADDRESS + 0x01U)
1225 #define PWM43HLD_ADDRESS (PWM43CR_ADDRESS + 0x01U)
1226 #define PWM44T1_ADDRESS (PWM43HLD_ADDRESS + 0x03U)
1227 #define PWM44T1H_ADDRESS (PWM44T1_ADDRESS + 0x00U)
1228 #define PWM44T1L_ADDRESS (PWM44T1H_ADDRESS + 0x01U)
1229 #define PWM44T2_ADDRESS (PWM44T1L_ADDRESS + 0x01U)
1230 #define PWM44T2H_ADDRESS (PWM44T2_ADDRESS + 0x00U)
1231 #define PWM44T2L_ADDRESS (PWM44T2H_ADDRESS + 0x01U)
1232 #define PWM44CR_ADDRESS (PWM44T2L_ADDRESS + 0x01U)
1233 #define PWM44HLD_ADDRESS (PWM44CR_ADDRESS + 0x01U)
1234 #define PWM45T1_ADDRESS (PWM44HLD_ADDRESS + 0x03U)
1235 #define PWM45T1H_ADDRESS (PWM45T1_ADDRESS + 0x00U)
1236 #define PWM45T1L_ADDRESS (PWM45T1H_ADDRESS + 0x01U)
1237 #define PWM45T2_ADDRESS (PWM45T1L_ADDRESS + 0x01U)
1238 #define PWM45T2H_ADDRESS (PWM45T2_ADDRESS + 0x00U)
1239 #define PWM45T2L_ADDRESS (PWM45T2H_ADDRESS + 0x01U)
1240 #define PWM45CR_ADDRESS (PWM45T2L_ADDRESS + 0x01U)
1241 #define PWM45HLD_ADDRESS (PWM45CR_ADDRESS + 0x01U)
1242 #define PWM46T1_ADDRESS (PWM45HLD_ADDRESS + 0x03U)
1243 #define PWM46T1H_ADDRESS (PWM46T1_ADDRESS + 0x00U)
1244 #define PWM46T1L_ADDRESS (PWM46T1H_ADDRESS + 0x01U)
1245 #define PWM46T2_ADDRESS (PWM46T1L_ADDRESS + 0x01U)
1246 #define PWM46T2H_ADDRESS (PWM46T2_ADDRESS + 0x00U)
1247 #define PWM46T2L_ADDRESS (PWM46T2H_ADDRESS + 0x01U)
1248 #define PWM46CR_ADDRESS (PWM46T2L_ADDRESS + 0x01U)
1249 #define PWM46HLD_ADDRESS (PWM46CR_ADDRESS + 0x01U)
1250 #define PWM47T1_ADDRESS (PWM46HLD_ADDRESS + 0x03U)
1251 #define PWM47T1H_ADDRESS (PWM47T1_ADDRESS + 0x00U)
1252 #define PWM47T1L_ADDRESS (PWM47T1H_ADDRESS + 0x01U)
1253 #define PWM47T2_ADDRESS (PWM47T1L_ADDRESS + 0x01U)
1254 #define PWM47T2H_ADDRESS (PWM47T2_ADDRESS + 0x00U)
1255 #define PWM47T2L_ADDRESS (PWM47T2H_ADDRESS + 0x01U)
1256 #define PWM47CR_ADDRESS (PWM47T2L_ADDRESS + 0x01U)
1257 #define PWM47HLD_ADDRESS (PWM47CR_ADDRESS + 0x01U)
1258 
1259 /* PWM5 control address define */
1260 #define PWM5_BASE 0xFCA0U
1261 #define PWM5C_ADDRESS (PWM5_BASE + 0x00U)
1262 #define PWM5CH_ADDRESS (PWM5C_ADDRESS + 0x00U)
1263 #define PWM5CL_ADDRESS (PWM5CH_ADDRESS + 0x01U)
1264 #define PWM5CKS_ADDRESS (PWM5CL_ADDRESS + 0x01U)
1265 #define PWM5TADC_ADDRESS (PWM5CKS_ADDRESS + 0x01U)
1266 #define PWM5TADCH_ADDRESS (PWM5TADC_ADDRESS + 0x00U)
1267 #define PWM5TADCL_ADDRESS (PWM5TADCH_ADDRESS + 0x01U)
1268 #define PWM5IF_ADDRESS (PWM5TADCL_ADDRESS + 0x01U)
1269 #define PWM5FDCR_ADDRESS (PWM5IF_ADDRESS + 0x01U)
1270 
1271 /* PWM5.0-PWM5.7 channal address define */
1272 #define PWM50T1_ADDRESS (PWM5FDCR_ADDRESS + 0x03U)
1273 #define PWM50T1H_ADDRESS (PWM50T1_ADDRESS + 0x00U)
1274 #define PWM50T1L_ADDRESS (PWM50T1H_ADDRESS + 0x01U)
1275 #define PWM50T2_ADDRESS (PWM50T1L_ADDRESS + 0x01U)
1276 #define PWM50T2H_ADDRESS (PWM50T2_ADDRESS + 0x00U)
1277 #define PWM50T2L_ADDRESS (PWM50T2H_ADDRESS + 0x01U)
1278 #define PWM50CR_ADDRESS (PWM50T2L_ADDRESS + 0x01U)
1279 #define PWM50HLD_ADDRESS (PWM50CR_ADDRESS + 0x01U)
1280 #define PWM51T1_ADDRESS (PWM50HLD_ADDRESS + 0x03U)
1281 #define PWM51T1H_ADDRESS (PWM51T1_ADDRESS + 0x00U)
1282 #define PWM51T1L_ADDRESS (PWM51T1H_ADDRESS + 0x01U)
1283 #define PWM51T2_ADDRESS (PWM51T1L_ADDRESS + 0x01U)
1284 #define PWM51T2H_ADDRESS (PWM51T2_ADDRESS + 0x00U)
1285 #define PWM51T2L_ADDRESS (PWM51T2H_ADDRESS + 0x01U)
1286 #define PWM51CR_ADDRESS (PWM51T2L_ADDRESS + 0x01U)
1287 #define PWM51HLD_ADDRESS (PWM51CR_ADDRESS + 0x01U)
1288 #define PWM52T1_ADDRESS (PWM51HLD_ADDRESS + 0x03U)
1289 #define PWM52T1H_ADDRESS (PWM52T1_ADDRESS + 0x00U)
1290 #define PWM52T1L_ADDRESS (PWM52T1H_ADDRESS + 0x01U)
1291 #define PWM52T2_ADDRESS (PWM52T1L_ADDRESS + 0x01U)
1292 #define PWM52T2H_ADDRESS (PWM52T2_ADDRESS + 0x00U)
1293 #define PWM52T2L_ADDRESS (PWM52T2H_ADDRESS + 0x01U)
1294 #define PWM52CR_ADDRESS (PWM52T2L_ADDRESS + 0x01U)
1295 #define PWM52HLD_ADDRESS (PWM52CR_ADDRESS + 0x01U)
1296 #define PWM53T1_ADDRESS (PWM52HLD_ADDRESS + 0x03U)
1297 #define PWM53T1H_ADDRESS (PWM53T1_ADDRESS + 0x00U)
1298 #define PWM53T1L_ADDRESS (PWM53T1H_ADDRESS + 0x01U)
1299 #define PWM53T2_ADDRESS (PWM53T1L_ADDRESS + 0x01U)
1300 #define PWM53T2H_ADDRESS (PWM53T2_ADDRESS + 0x00U)
1301 #define PWM53T2L_ADDRESS (PWM53T2H_ADDRESS + 0x01U)
1302 #define PWM53CR_ADDRESS (PWM53T2L_ADDRESS + 0x01U)
1303 #define PWM53HLD_ADDRESS (PWM53CR_ADDRESS + 0x01U)
1304 #define PWM54T1_ADDRESS (PWM53HLD_ADDRESS + 0x03U)
1305 #define PWM54T1H_ADDRESS (PWM54T1_ADDRESS + 0x00U)
1306 #define PWM54T1L_ADDRESS (PWM54T1H_ADDRESS + 0x01U)
1307 #define PWM54T2_ADDRESS (PWM54T1L_ADDRESS + 0x01U)
1308 #define PWM54T2H_ADDRESS (PWM54T2_ADDRESS + 0x00U)
1309 #define PWM54T2L_ADDRESS (PWM54T2H_ADDRESS + 0x01U)
1310 #define PWM54CR_ADDRESS (PWM54T2L_ADDRESS + 0x01U)
1311 #define PWM54HLD_ADDRESS (PWM54CR_ADDRESS + 0x01U)
1312 #define PWM55T1_ADDRESS (PWM54HLD_ADDRESS + 0x03U)
1313 #define PWM55T1H_ADDRESS (PWM55T1_ADDRESS + 0x00U)
1314 #define PWM55T1L_ADDRESS (PWM55T1H_ADDRESS + 0x01U)
1315 #define PWM55T2_ADDRESS (PWM55T1L_ADDRESS + 0x01U)
1316 #define PWM55T2H_ADDRESS (PWM55T2_ADDRESS + 0x00U)
1317 #define PWM55T2L_ADDRESS (PWM55T2H_ADDRESS + 0x01U)
1318 #define PWM55CR_ADDRESS (PWM55T2L_ADDRESS + 0x01U)
1319 #define PWM55HLD_ADDRESS (PWM55CR_ADDRESS + 0x01U)
1320 #define PWM56T1_ADDRESS (PWM55HLD_ADDRESS + 0x03U)
1321 #define PWM56T1H_ADDRESS (PWM56T1_ADDRESS + 0x00U)
1322 #define PWM56T1L_ADDRESS (PWM56T1H_ADDRESS + 0x01U)
1323 #define PWM56T2_ADDRESS (PWM56T1L_ADDRESS + 0x01U)
1324 #define PWM56T2H_ADDRESS (PWM56T2_ADDRESS + 0x00U)
1325 #define PWM56T2L_ADDRESS (PWM56T2H_ADDRESS + 0x01U)
1326 #define PWM56CR_ADDRESS (PWM56T2L_ADDRESS + 0x01U)
1327 #define PWM56HLD_ADDRESS (PWM56CR_ADDRESS + 0x01U)
1328 #define PWM57T1_ADDRESS (PWM56HLD_ADDRESS + 0x03U)
1329 #define PWM57T1H_ADDRESS (PWM57T1_ADDRESS + 0x00U)
1330 #define PWM57T1L_ADDRESS (PWM57T1H_ADDRESS + 0x01U)
1331 #define PWM57T2_ADDRESS (PWM57T1L_ADDRESS + 0x01U)
1332 #define PWM57T2H_ADDRESS (PWM57T2_ADDRESS + 0x00U)
1333 #define PWM57T2L_ADDRESS (PWM57T2H_ADDRESS + 0x01U)
1334 #define PWM57CR_ADDRESS (PWM57T2L_ADDRESS + 0x01U)
1335 #define PWM57HLD_ADDRESS (PWM57CR_ADDRESS + 0x01U)
1336 
1337 /* Register bit define */
1338 /* PWMSET */
1339 #define ENGLBSET 0x80
1340 #define PWMRST 0x40
1341 #define ENPWM5 0x20
1342 #define ENPWM4 0x10
1343 #define ENPWM3 0x08
1344 #define ENPWM2 0x04
1345 #define ENPWM1 0x02
1346 #define ENPWM0 0x01
1347 
1348 /* PWMCFGxx bits */
1349 #define PWMCBIF135 0x80
1350 #define EPWMCBI135 0x40
1351 #define FLTPS 0x20
1352 #define PWMCEN135 0x10
1353 #define PWMCBIF024 0x08
1354 #define EPWMCBI024 0x04
1355 #define ENPWMTA024 0x02
1356 #define PWMCEN024 0x01
1357 
1358 /* PWMnIF */
1359 #define C7IF 0x80
1360 #define C6IF 0x40
1361 #define C5IF 0x20
1362 #define C4IF 0x10
1363 #define C3IF 0x08
1364 #define C2IF 0x04
1365 #define C1IF 0x02
1366 #define C0IF 0x01
1367 
1368 /* PWMnFDCR */
1369 #define INVCMP 0x80
1370 #define INVIO 0x40
1371 #define ENFD 0x20
1372 #define FLTFLIO 0x10
1373 #define EFDI 0x08
1374 #define FDCMP 0x04
1375 #define FDIO 0x02
1376 #define FDIF 0x01
1377 
1378 /* PWMniCR */
1379 #define ENO 0x80
1380 #define INI 0x40
1381 #define ENI 0x04
1382 #define ENT2I 0x02
1383 #define ENT1I 0x01
1384 
1385 
1386 /*** 增强型 PWM 配置寄存器(PWMCFGn) ***/
1387 sfr PWMCFG01 = PWMCFG01_ADDRESS;
1388 sfr PWMCFG23 = PWMCFG23_ADDRESS;
1389 sfr PWMCFG45 = PWMCFG45_ADDRESS;
1390 
1391 /*--------------------------------------------------------
1392 | @Description: SPI peripherals |
1393 --------------------------------------------------------*/
1394 
1395 /* Base address */
1396 #define SPSTAT_ADDRESS 0xCDU
1397 #define SPCTL_ADDRESS 0xCEU
1398 #define SPDAT_ADDRESS 0xCFU
1399 
1400 /* SPSTAT */
1401 #define SPIF 0x80
1402 #define WCOL 0x40
1403 
1404 /* SPCTL */
1405 #define SSIG 0x80
1406 #define SPEN 0x40
1407 #define DORD 0x20
1408 #define MSTR 0x10
1409 #define CPOL 0x08
1410 #define CPHA 0x04
1411 
1412 /* SPI register */
1413 sfr SPSTAT = SPSTAT_ADDRESS;
1414 sfr SPCTL = SPCTL_ADDRESS;
1415 sfr SPDAT = SPDAT_ADDRESS;
1416 
1417 /*--------------------------------------------------------
1418 | @Description: I2C peripherals |
1419 --------------------------------------------------------*/
1420 
1421 /* Base address */
1422 #define I2C_BASE 0xFE80U
1423 #define I2CCFG_ADDRESS (I2C_BASE + 0x00U)
1424 #define I2CMSCR_ADDRESS (I2C_BASE + 0x01U)
1425 #define I2CMSST_ADDRESS (I2C_BASE + 0x02U)
1426 #define I2CSLCR_ADDRESS (I2C_BASE + 0x03U)
1427 #define I2CSLST_ADDRESS (I2C_BASE + 0x04U)
1428 #define I2CSLADR_ADDRESS (I2C_BASE + 0x05U)
1429 #define I2CTXD_ADDRESS (I2C_BASE + 0x06U)
1430 #define I2CRXD_ADDRESS (I2C_BASE + 0x07U)
1431 
1432 /* I2CCFG */
1433 #define ENI2C 0x80
1434 #define MSSL 0x40
1435 
1436 /* I2CMSCR */
1437 #define EMSI 0x80
1438 
1439 /* I2CMSST */
1440 #define MSBUSY 0x80
1441 #define MSIF 0x40
1442 #define MSACKI 0x02
1443 #define MSACKO 0x01
1444 
1445 /* I2CSLCR */
1446 #define ESTAI 0x40
1447 #define ERXI 0x20
1448 #define ETXI 0x10
1449 #define ESTOI 0x08
1450 #define SLRST 0x01
1451 
1452 /* I2CSLST */
1453 #define SLBUSY 0x80
1454 #define STAIF 0x40
1455 #define RXIF 0x20
1456 #define TXIF 0x10
1457 #define STOIF 0x08
1458 #define TXING 0x04
1459 #define SLACKI 0x02
1460 #define SLACKO 0x01
1461 
1462 /* SPI register */
1463 
1464 #define I2CCFG (*(__IO uint8_t xdata *) I2CCFG_ADDRESS)
1465 #define I2CMSCR (*(__IO uint8_t xdata *) I2CMSCR_ADDRESS)
1466 #define I2CMSST (*(__IO uint8_t xdata *) I2CMSST_ADDRESS)
1467 #define I2CSLCR (*(__IO uint8_t xdata *) I2CSLCR_ADDRESS)
1468 #define I2CSLST (*(__IO uint8_t xdata * )I2CSLST_ADDRESS)
1469 #define I2CSLADR (*(__IO uint8_t xdata *)I2CSLADR_ADDRESS)
1470 #define I2CTXD (*(__IO uint8_t xdata *) I2CTXD_ADDRESS)
1471 #define I2CRXD (*(__IO uint8_t xdata *) I2CRXD_ADDRESS)
1472 
1473 /*--------------------------------------------------------
1474 | @Description: MDU16 peripherals |
1475 --------------------------------------------------------*/
1476 
1477 typedef struct
1478 {
1479  __IO uint8_t MD3_REG; /*---- MDU Divisor data register */
1480 
1481  __IO uint8_t MD2_REG; /*---- MDU Divisor data register */
1482 
1483  __IO uint8_t MD1_REG; /*---- MDU Divisor data register */
1484 
1485  __IO uint8_t MD0_REG; /*---- MDU Divisor data register */
1486 
1487  __IO uint8_t MD5_REG; /*---- MDU Divisor data register */
1488 
1489  __IO uint8_t MD4_REG; /*---- MDU Divisor data register */
1490 
1491  __IO uint8_t ARCON_REG; /*----MDU module data registe */
1492 
1493  __IO uint8_t OPCON_REG; /*----MDU control data registe */
1494 
1495 } MDU16_TypeDef;
1496 
1497 #define MDU16_BASE 0xFCF0U
1498 
1499 #define MD3_ADDRESS (MDU16_BASE)
1500 #define MD2_ADDRESS (MDU16_BASE + 0x0001U)
1501 #define MD1_ADDRESS (MDU16_BASE + 0x0002U)
1502 #define MD0_ADDRESS (MDU16_BASE + 0x0003U)
1503 #define MD5_ADDRESS (MDU16_BASE + 0x0004U)
1504 #define MD4_ADDRESS (MDU16_BASE + 0x0005U)
1505 #define ARCON_ADDRESS (MDU16_BASE + 0x0006U)
1506 #define OPCON_ADDRESS (MDU16_BASE + 0x0007U)
1507 
1508 /* Define type of MDU16 */
1509 
1510 #define MDU16 (* (MDU16_TypeDef xdata *) MDU16_BASE)
1511 
1512 #define MD3U32 (*(__IO uint32_t xdata *) MD3_ADDRESS)
1513 #define MD3U16 (*(__IO uint16_t xdata *) MD3_ADDRESS)
1514 #define MD1U16 (*(__IO uint16_t xdata *) MD1_ADDRESS)
1515 #define MD5U16 (*(__IO uint16_t xdata *) MD5_ADDRESS)
1516 
1517 #define MD3 (*(__IO uint8_t xdata *) MD3_ADDRESS)
1518 #define MD2 (*(__IO uint8_t xdata *) MD2_ADDRESS)
1519 #define MD1 (*(__IO uint8_t xdata *) MD1_ADDRESS)
1520 #define MD0 (*(__IO uint8_t xdata *) MD0_ADDRESS)
1521 #define MD5 (*(__IO uint8_t xdata *) MD5_ADDRESS)
1522 #define MD4 (*(__IO uint8_t xdata *) MD4_ADDRESS)
1523 
1524 #define ARCON (*(__IO uint8_t xdata *) ARCON_ADDRESS)
1525 #define OPCON (*(__IO uint8_t xdata *) OPCON_ADDRESS)
1526 
1527 #endif
1528 /*-----------------------------------------------------------------------
1529 | END OF FLIE (C) COPYRIGHT Gevico Electronics |
1530 -----------------------------------------------------------------------*/
ELL_TYPE.h
uint8_t
unsigned char uint8_t
Definition: ELL_TYPE.h:72
__IO
#define __IO
Definition: ELL_TYPE.h:106
P4M0
sfr P4M0
Definition: STC8Gx_REG.h:432
P50
sbit P50
Definition: STC8Gx_REG.h:390
P06
sbit P06
Definition: STC8Gx_REG.h:353
P7M0
sfr P7M0
Definition: STC8Gx_REG.h:435
CY
sbit CY
Definition: STC8Gx_REG.h:49
T0L
sfr T0L
Definition: STC8Gx_REG.h:567
PER_SW2_ADDRESS
#define PER_SW2_ADDRESS
Definition: STC8Gx_REG.h:73
F1
sbit F1
Definition: STC8Gx_REG.h:55
P6M1_ADDRESS
#define P6M1_ADDRESS
Definition: STC8Gx_REG.h:276
P76
sbit P76
Definition: STC8Gx_REG.h:414
T4L
sfr T4L
Definition: STC8Gx_REG.h:577
ISP_ADDRH
sfr ISP_ADDRH
Definition: STC8Gx_REG.h:774
CMOD_ADDRESS
#define CMOD_ADDRESS
Definition: STC8Gx_REG.h:786
DPH
sfr DPH
Definition: STC8Gx_REG.h:59
P1
sfr P1
Definition: STC8Gx_REG.h:338
P36
sbit P36
Definition: STC8Gx_REG.h:381
IAP_TRIG_ADDRESS
#define IAP_TRIG_ADDRESS
Definition: STC8Gx_REG.h:741
CMPCR1_ADDRESS
#define CMPCR1_ADDRESS
Definition: STC8Gx_REG.h:683
CCON
sfr CCON
Definition: STC8Gx_REG.h:834
AUXR_ADDRESS
#define AUXR_ADDRESS
Definition: STC8Gx_REG.h:70
TL1
sfr TL1
Definition: STC8Gx_REG.h:572
IPH
sfr IPH
Definition: STC8Gx_REG.h:200
P0M0_ADDRESS
#define P0M0_ADDRESS
Definition: STC8Gx_REG.h:279
P0
sfr P0
Definition: STC8Gx_REG.h:337
P70
sbit P70
Definition: STC8Gx_REG.h:408
PADC
sbit PADC
Definition: STC8Gx_REG.h:219
IP3_ADDRESS
#define IP3_ADDRESS
Definition: STC8Gx_REG.h:169
P2_ADDRESS
#define P2_ADDRESS
Definition: STC8Gx_REG.h:262
ACC
sfr ACC
Definition: STC8Gx_REG.h:46
WDT_CONTR
sfr WDT_CONTR
Definition: STC8Gx_REG.h:506
S4BUF_ADDRESS
#define S4BUF_ADDRESS
Definition: STC8Gx_REG.h:622
CCAP1H
sfr CCAP1H
Definition: STC8Gx_REG.h:846
P5
sfr P5
Definition: STC8Gx_REG.h:342
IP3H
sfr IP3H
Definition: STC8Gx_REG.h:204
PX0
sbit PX0
Definition: STC8Gx_REG.h:224
P24
sbit P24
Definition: STC8Gx_REG.h:370
P10
sbit P10
Definition: STC8Gx_REG.h:357
SPCTL
sfr SPCTL
Definition: STC8Gx_REG.h:1414
P_SW2
sfr P_SW2
Definition: STC8Gx_REG.h:79
WKTCL
sfr WKTCL
Definition: STC8Gx_REG.h:582
P13
sbit P13
Definition: STC8Gx_REG.h:360
SPDAT
sfr SPDAT
Definition: STC8Gx_REG.h:1415
P0M1
sfr P0M1
Definition: STC8Gx_REG.h:418
P40
sbit P40
Definition: STC8Gx_REG.h:384
EX1
sbit EX1
Definition: STC8Gx_REG.h:213
TR0
sbit TR0
Definition: STC8Gx_REG.h:588
IRCBAND
sfr IRCBAND
Definition: STC8Gx_REG.h:139
P4
sfr P4
Definition: STC8Gx_REG.h:341
P6M0_ADDRESS
#define P6M0_ADDRESS
Definition: STC8Gx_REG.h:285
CCAP1L
sfr CCAP1L
Definition: STC8Gx_REG.h:842
P66
sbit P66
Definition: STC8Gx_REG.h:405
CCAP0L_ADDRESS
#define CCAP0L_ADDRESS
Definition: STC8Gx_REG.h:792
ISP_DATA
sfr ISP_DATA
Definition: STC8Gx_REG.h:773
IAP_ADDRH_ADDRESS
#define IAP_ADDRH_ADDRESS
Definition: STC8Gx_REG.h:738
T1L_ADDRESS
#define T1L_ADDRESS
Definition: STC8Gx_REG.h:518
CMPCR1
sfr CMPCR1
Definition: STC8Gx_REG.h:701
P77
sbit P77
Definition: STC8Gx_REG.h:415
IAP_CONTR
sfr IAP_CONTR
Definition: STC8Gx_REG.h:770
PCA_PWM0
sfr PCA_PWM0
Definition: STC8Gx_REG.h:848
PT1
sbit PT1
Definition: STC8Gx_REG.h:221
BUS_SPEED
sfr BUS_SPEED
Definition: STC8Gx_REG.h:438
SM0
sbit SM0
Definition: STC8Gx_REG.h:669
CL_ADDRESS
#define CL_ADDRESS
Definition: STC8Gx_REG.h:787
DPL1
sfr DPL1
Definition: STC8Gx_REG.h:62
CCAPM0
sfr CCAPM0
Definition: STC8Gx_REG.h:838
P14
sbit P14
Definition: STC8Gx_REG.h:361
ADCCFG_ADDRESS
#define ADCCFG_ADDRESS
Definition: STC8Gx_REG.h:713
P34
sbit P34
Definition: STC8Gx_REG.h:379
PWMCFG01_ADDRESS
#define PWMCFG01_ADDRESS
Definition: STC8Gx_REG.h:865
S3CON
sfr S3CON
Definition: STC8Gx_REG.h:662
P51
sbit P51
Definition: STC8Gx_REG.h:391
P31
sbit P31
Definition: STC8Gx_REG.h:376
P67
sbit P67
Definition: STC8Gx_REG.h:406
F0
sbit F0
Definition: STC8Gx_REG.h:51
P33
sbit P33
Definition: STC8Gx_REG.h:378
P73
sbit P73
Definition: STC8Gx_REG.h:411
ADC_RESL_ADDRESS
#define ADC_RESL_ADDRESS
Definition: STC8Gx_REG.h:712
P01
sbit P01
Definition: STC8Gx_REG.h:348
ISP_TRIG
sfr ISP_TRIG
Definition: STC8Gx_REG.h:777
PPCA
sbit PPCA
Definition: STC8Gx_REG.h:217
P60
sbit P60
Definition: STC8Gx_REG.h:399
P44
sbit P44
Definition: STC8Gx_REG.h:388
TCON_ADDRESS
#define TCON_ADDRESS
Definition: STC8Gx_REG.h:515
IT1
sbit IT1
Definition: STC8Gx_REG.h:607
ADC_CONTR_ADDRESS
#define ADC_CONTR_ADDRESS
Definition: STC8Gx_REG.h:709
SP
sfr SP
Definition: STC8Gx_REG.h:57
P00
sbit P00
Definition: STC8Gx_REG.h:347
TR1
sbit TR1
Definition: STC8Gx_REG.h:586
RSTCFG_ADDRESS
#define RSTCFG_ADDRESS
Definition: STC8Gx_REG.h:503
P5M1_ADDRESS
#define P5M1_ADDRESS
Definition: STC8Gx_REG.h:275
T4T3M
sfr T4T3M
Definition: STC8Gx_REG.h:575
CMPCR2
sfr CMPCR2
Definition: STC8Gx_REG.h:702
PWMCFG45_ADDRESS
#define PWMCFG45_ADDRESS
Definition: STC8Gx_REG.h:867
P41
sbit P41
Definition: STC8Gx_REG.h:385
LIRTRIM_ADDRESS
#define LIRTRIM_ADDRESS
Definition: STC8Gx_REG.h:110
OV
sbit OV
Definition: STC8Gx_REG.h:54
P15
sbit P15
Definition: STC8Gx_REG.h:362
P32
sbit P32
Definition: STC8Gx_REG.h:377
TL0
sfr TL0
Definition: STC8Gx_REG.h:571
P07
sbit P07
Definition: STC8Gx_REG.h:354
CCF0
sbit CCF0
Definition: STC8Gx_REG.h:857
S2BUF_ADDRESS
#define S2BUF_ADDRESS
Definition: STC8Gx_REG.h:618
TH1
sfr TH1
Definition: STC8Gx_REG.h:574
IP2H
sfr IP2H
Definition: STC8Gx_REG.h:202
S4CON
sfr S4CON
Definition: STC8Gx_REG.h:664
PER_SW1_ADDRESS
#define PER_SW1_ADDRESS
Definition: STC8Gx_REG.h:72
CCAP1L_ADDRESS
#define CCAP1L_ADDRESS
Definition: STC8Gx_REG.h:793
CCAP2H_ADDRESS
#define CCAP2H_ADDRESS
Definition: STC8Gx_REG.h:797
INTCLKO
sfr INTCLKO
Definition: STC8Gx_REG.h:205
T4H
sfr T4H
Definition: STC8Gx_REG.h:576
CCAP1H_ADDRESS
#define CCAP1H_ADDRESS
Definition: STC8Gx_REG.h:796
CCF1
sbit CCF1
Definition: STC8Gx_REG.h:856
ISP_CMD
sfr ISP_CMD
Definition: STC8Gx_REG.h:776
P4M1
sfr P4M1
Definition: STC8Gx_REG.h:422
PCA_PWM1_ADDRESS
#define PCA_PWM1_ADDRESS
Definition: STC8Gx_REG.h:799
P0M1_ADDRESS
#define P0M1_ADDRESS
Definition: STC8Gx_REG.h:270
RS1
sbit RS1
Definition: STC8Gx_REG.h:52
T2L
sfr T2L
Definition: STC8Gx_REG.h:581
IAP_CMD_ADDRESS
#define IAP_CMD_ADDRESS
Definition: STC8Gx_REG.h:740
B
sfr B
Definition: STC8Gx_REG.h:47
S2CON_ADDRESS
#define S2CON_ADDRESS
Definition: STC8Gx_REG.h:617
LIRTRIM
sfr LIRTRIM
Definition: STC8Gx_REG.h:141
CCAP0L
sfr CCAP0L
Definition: STC8Gx_REG.h:841
CMPCR2_ADDRESS
#define CMPCR2_ADDRESS
Definition: STC8Gx_REG.h:684
P72
sbit P72
Definition: STC8Gx_REG.h:410
P6_ADDRESS
#define P6_ADDRESS
Definition: STC8Gx_REG.h:266
T4H_ADDRESS
#define T4H_ADDRESS
Definition: STC8Gx_REG.h:522
IE1
sbit IE1
Definition: STC8Gx_REG.h:589
P2M0
sfr P2M0
Definition: STC8Gx_REG.h:430
P65
sbit P65
Definition: STC8Gx_REG.h:404
PCA_PWM1
sfr PCA_PWM1
Definition: STC8Gx_REG.h:849
P5M0
sfr P5M0
Definition: STC8Gx_REG.h:433
P23
sbit P23
Definition: STC8Gx_REG.h:369
WKTCH_ADDRESS
#define WKTCH_ADDRESS
Definition: STC8Gx_REG.h:529
P3M0
sfr P3M0
Definition: STC8Gx_REG.h:431
IAP_CONTR_ADDRESS
#define IAP_CONTR_ADDRESS
Definition: STC8Gx_REG.h:742
CCAP0H
sfr CCAP0H
Definition: STC8Gx_REG.h:845
IP2
sfr IP2
Definition: STC8Gx_REG.h:201
CCAPM2_ADDRESS
#define CCAPM2_ADDRESS
Definition: STC8Gx_REG.h:791
IPH_ADDRESS
#define IPH_ADDRESS
Definition: STC8Gx_REG.h:166
P6
sfr P6
Definition: STC8Gx_REG.h:343
T3L_ADDRESS
#define T3L_ADDRESS
Definition: STC8Gx_REG.h:525
ADC_RES
sfr ADC_RES
Definition: STC8Gx_REG.h:726
P20
sbit P20
Definition: STC8Gx_REG.h:366
CCAPM2
sfr CCAPM2
Definition: STC8Gx_REG.h:840
P6M1
sfr P6M1
Definition: STC8Gx_REG.h:424
SPSTAT
sfr SPSTAT
Definition: STC8Gx_REG.h:1413
IE_ADDRESS
#define IE_ADDRESS
Definition: STC8Gx_REG.h:163
IE
sfr IE
Definition: STC8Gx_REG.h:197
BUS_SPEED_ADDRESS
#define BUS_SPEED_ADDRESS
Definition: STC8Gx_REG.h:249
TA
sfr TA
Definition: STC8Gx_REG.h:60
P_SW1
sfr P_SW1
Definition: STC8Gx_REG.h:78
P2
sfr P2
Definition: STC8Gx_REG.h:339
P53
sbit P53
Definition: STC8Gx_REG.h:393
SM1
sbit SM1
Definition: STC8Gx_REG.h:670
PCA_PWM2_ADDRESS
#define PCA_PWM2_ADDRESS
Definition: STC8Gx_REG.h:800
P71
sbit P71
Definition: STC8Gx_REG.h:409
ISP_ADDRH_ADDRESS
#define ISP_ADDRH_ADDRESS
Definition: STC8Gx_REG.h:746
PX1
sbit PX1
Definition: STC8Gx_REG.h:222
ET0
sbit ET0
Definition: STC8Gx_REG.h:214
SADEN_ADDRESS
#define SADEN_ADDRESS
Definition: STC8Gx_REG.h:624
IP
sfr IP
Definition: STC8Gx_REG.h:199
ADCCFG
sfr ADCCFG
Definition: STC8Gx_REG.h:728
DPS
sfr DPS
Definition: STC8Gx_REG.h:61
ISP_CONTR_ADDRESS
#define ISP_CONTR_ADDRESS
Definition: STC8Gx_REG.h:750
S3BUF_ADDRESS
#define S3BUF_ADDRESS
Definition: STC8Gx_REG.h:620
P62
sbit P62
Definition: STC8Gx_REG.h:401
T1H_ADDRESS
#define T1H_ADDRESS
Definition: STC8Gx_REG.h:520
ISP_CONTR
sfr ISP_CONTR
Definition: STC8Gx_REG.h:778
P3_ADDRESS
#define P3_ADDRESS
Definition: STC8Gx_REG.h:263
P7M1
sfr P7M1
Definition: STC8Gx_REG.h:425
P37
sbit P37
Definition: STC8Gx_REG.h:382
P42
sbit P42
Definition: STC8Gx_REG.h:386
DPL
sfr DPL
Definition: STC8Gx_REG.h:58
TI
sbit TI
Definition: STC8Gx_REG.h:675
TMOD_ADDRESS
#define TMOD_ADDRESS
Definition: STC8Gx_REG.h:516
IE0
sbit IE0
Definition: STC8Gx_REG.h:590
T3H_ADDRESS
#define T3H_ADDRESS
Definition: STC8Gx_REG.h:524
P27
sbit P27
Definition: STC8Gx_REG.h:373
IE2_ADDRESS
#define IE2_ADDRESS
Definition: STC8Gx_REG.h:164
TF1
sbit TF1
Definition: STC8Gx_REG.h:585
PCA_PWM0_ADDRESS
#define PCA_PWM0_ADDRESS
Definition: STC8Gx_REG.h:798
P52
sbit P52
Definition: STC8Gx_REG.h:392
P4_ADDRESS
#define P4_ADDRESS
Definition: STC8Gx_REG.h:264
T4T3M_ADDRESS
#define T4T3M_ADDRESS
Definition: STC8Gx_REG.h:521
IAP_DATA
sfr IAP_DATA
Definition: STC8Gx_REG.h:765
P25
sbit P25
Definition: STC8Gx_REG.h:371
WDT_ADDRESS
#define WDT_ADDRESS
Definition: STC8Gx_REG.h:502
VOCTRL_ADDRESS
#define VOCTRL_ADDRESS
Definition: STC8Gx_REG.h:152
P26
sbit P26
Definition: STC8Gx_REG.h:372
TF0
sbit TF0
Definition: STC8Gx_REG.h:587
P74
sbit P74
Definition: STC8Gx_REG.h:412
PWMCFG45
sfr PWMCFG45
Definition: STC8Gx_REG.h:1389
ES
sbit ES
Definition: STC8Gx_REG.h:211
PCON
sfr PCON
Definition: STC8Gx_REG.h:155
S2CON
sfr S2CON
Definition: STC8Gx_REG.h:660
ISP_DATA_ADDRESS
#define ISP_DATA_ADDRESS
Definition: STC8Gx_REG.h:745
SCON_ADDRESS
#define SCON_ADDRESS
Definition: STC8Gx_REG.h:615
CCAP2H
sfr CCAP2H
Definition: STC8Gx_REG.h:847
T3H
sfr T3H
Definition: STC8Gx_REG.h:578
IAP_DATA_ADDRESS
#define IAP_DATA_ADDRESS
Definition: STC8Gx_REG.h:737
P2M0_ADDRESS
#define P2M0_ADDRESS
Definition: STC8Gx_REG.h:281
P2M1
sfr P2M1
Definition: STC8Gx_REG.h:420
ISP_CMD_ADDRESS
#define ISP_CMD_ADDRESS
Definition: STC8Gx_REG.h:748
P43
sbit P43
Definition: STC8Gx_REG.h:387
P05
sbit P05
Definition: STC8Gx_REG.h:352
T4L_ADDRESS
#define T4L_ADDRESS
Definition: STC8Gx_REG.h:523
SADDR
sfr SADDR
Definition: STC8Gx_REG.h:666
P55
sbit P55
Definition: STC8Gx_REG.h:395
P1_ADDRESS
#define P1_ADDRESS
Definition: STC8Gx_REG.h:261
ET1
sbit ET1
Definition: STC8Gx_REG.h:212
AUXR
sfr AUXR
Definition: STC8Gx_REG.h:76
PS
sbit PS
Definition: STC8Gx_REG.h:220
S4BUF
sfr S4BUF
Definition: STC8Gx_REG.h:665
ISP_ADDRL_ADDRESS
#define ISP_ADDRL_ADDRESS
Definition: STC8Gx_REG.h:747
IAP_ADDRL
sfr IAP_ADDRL
Definition: STC8Gx_REG.h:767
EADC
sbit EADC
Definition: STC8Gx_REG.h:210
CCAPM1
sfr CCAPM1
Definition: STC8Gx_REG.h:839
CL
sfr CL
Definition: STC8Gx_REG.h:836
P5M0_ADDRESS
#define P5M0_ADDRESS
Definition: STC8Gx_REG.h:284
P1M0
sfr P1M0
Definition: STC8Gx_REG.h:429
P12
sbit P12
Definition: STC8Gx_REG.h:359
P75
sbit P75
Definition: STC8Gx_REG.h:413
P16
sbit P16
Definition: STC8Gx_REG.h:363
CH
sfr CH
Definition: STC8Gx_REG.h:837
PT0
sbit PT0
Definition: STC8Gx_REG.h:223
AUXINTIF
sfr AUXINTIF
Definition: STC8Gx_REG.h:206
P02
sbit P02
Definition: STC8Gx_REG.h:349
IT0
sbit IT0
Definition: STC8Gx_REG.h:606
P5M1
sfr P5M1
Definition: STC8Gx_REG.h:423
P4M0_ADDRESS
#define P4M0_ADDRESS
Definition: STC8Gx_REG.h:283
RB8
sbit RB8
Definition: STC8Gx_REG.h:674
P64
sbit P64
Definition: STC8Gx_REG.h:403
P3M1
sfr P3M1
Definition: STC8Gx_REG.h:421
S2BUF
sfr S2BUF
Definition: STC8Gx_REG.h:661
WKTCL_ADDRESS
#define WKTCL_ADDRESS
Definition: STC8Gx_REG.h:528
S3CON_ADDRESS
#define S3CON_ADDRESS
Definition: STC8Gx_REG.h:619
RSTCFG
sfr RSTCFG
Definition: STC8Gx_REG.h:508
P1M1
sfr P1M1
Definition: STC8Gx_REG.h:419
ELVD
sbit ELVD
Definition: STC8Gx_REG.h:209
T0H_ADDRESS
#define T0H_ADDRESS
Definition: STC8Gx_REG.h:519
ADC_CONTR
sfr ADC_CONTR
Definition: STC8Gx_REG.h:725
ADC_RESH_ADDRESS
#define ADC_RESH_ADDRESS
Definition: STC8Gx_REG.h:711
IAP_ADDRH
sfr IAP_ADDRH
Definition: STC8Gx_REG.h:766
IP2H_ADDRESS
#define IP2H_ADDRESS
Definition: STC8Gx_REG.h:168
ISP_TRIG_ADDRESS
#define ISP_TRIG_ADDRESS
Definition: STC8Gx_REG.h:749
CF
sbit CF
Definition: STC8Gx_REG.h:852
P1M1_ADDRESS
#define P1M1_ADDRESS
Definition: STC8Gx_REG.h:271
TMOD
sfr TMOD
Definition: STC8Gx_REG.h:566
T3L
sfr T3L
Definition: STC8Gx_REG.h:579
P11
sbit P11
Definition: STC8Gx_REG.h:358
TB8
sbit TB8
Definition: STC8Gx_REG.h:673
P4M1_ADDRESS
#define P4M1_ADDRESS
Definition: STC8Gx_REG.h:274
P63
sbit P63
Definition: STC8Gx_REG.h:402
PSW
sfr PSW
Definition: STC8Gx_REG.h:48
INTCLKO_ADDRESS
#define INTCLKO_ADDRESS
Definition: STC8Gx_REG.h:171
AUXINTIF_ADDRESS
#define AUXINTIF_ADDRESS
Definition: STC8Gx_REG.h:172
IE2
sfr IE2
Definition: STC8Gx_REG.h:198
CCF2
sbit CCF2
Definition: STC8Gx_REG.h:855
T0L_ADDRESS
#define T0L_ADDRESS
Definition: STC8Gx_REG.h:517
SBUF
sfr SBUF
Definition: STC8Gx_REG.h:659
ADC_RESL
sfr ADC_RESL
Definition: STC8Gx_REG.h:727
P7M0_ADDRESS
#define P7M0_ADDRESS
Definition: STC8Gx_REG.h:286
IRTRIM_ADDRESS
#define IRTRIM_ADDRESS
Definition: STC8Gx_REG.h:111
IAP_TPS_ADDRESS
#define IAP_TPS_ADDRESS
Definition: STC8Gx_REG.h:743
IRCBAND_ADDRESS
#define IRCBAND_ADDRESS
Definition: STC8Gx_REG.h:109
SPCTL_ADDRESS
#define SPCTL_ADDRESS
Definition: STC8Gx_REG.h:1397
VOCTRL
sfr VOCTRL
Definition: STC8Gx_REG.h:156
RS0
sbit RS0
Definition: STC8Gx_REG.h:53
T1L
sfr T1L
Definition: STC8Gx_REG.h:568
TH0
sfr TH0
Definition: STC8Gx_REG.h:573
AUXR2_ADDRESS
#define AUXR2_ADDRESS
Definition: STC8Gx_REG.h:71
RI
sbit RI
Definition: STC8Gx_REG.h:676
P0M0
sfr P0M0
Definition: STC8Gx_REG.h:428
CCAP0H_ADDRESS
#define CCAP0H_ADDRESS
Definition: STC8Gx_REG.h:795
P04
sbit P04
Definition: STC8Gx_REG.h:351
TCON
sfr TCON
Definition: STC8Gx_REG.h:565
AC
sbit AC
Definition: STC8Gx_REG.h:50
P54
sbit P54
Definition: STC8Gx_REG.h:394
REN
sbit REN
Definition: STC8Gx_REG.h:672
CCAP2L
sfr CCAP2L
Definition: STC8Gx_REG.h:843
P35
sbit P35
Definition: STC8Gx_REG.h:380
P3M1_ADDRESS
#define P3M1_ADDRESS
Definition: STC8Gx_REG.h:273
P1M0_ADDRESS
#define P1M0_ADDRESS
Definition: STC8Gx_REG.h:280
T1H
sfr T1H
Definition: STC8Gx_REG.h:570
PCA_PWM2
sfr PCA_PWM2
Definition: STC8Gx_REG.h:850
P7_ADDRESS
#define P7_ADDRESS
Definition: STC8Gx_REG.h:267
SPSTAT_ADDRESS
#define SPSTAT_ADDRESS
Definition: STC8Gx_REG.h:1396
P3M0_ADDRESS
#define P3M0_ADDRESS
Definition: STC8Gx_REG.h:282
IP_ADDRESS
#define IP_ADDRESS
Definition: STC8Gx_REG.h:165
IAP_TPS
sfr IAP_TPS
Definition: STC8Gx_REG.h:771
SBUF_ADDRESS
#define SBUF_ADDRESS
Definition: STC8Gx_REG.h:616
CCAPM0_ADDRESS
#define CCAPM0_ADDRESS
Definition: STC8Gx_REG.h:789
PWMCFG23
sfr PWMCFG23
Definition: STC8Gx_REG.h:1388
WKTCH
sfr WKTCH
Definition: STC8Gx_REG.h:583
P7
sfr P7
Definition: STC8Gx_REG.h:344
P5_ADDRESS
#define P5_ADDRESS
Definition: STC8Gx_REG.h:265
P21
sbit P21
Definition: STC8Gx_REG.h:367
SPDAT_ADDRESS
#define SPDAT_ADDRESS
Definition: STC8Gx_REG.h:1398
PLVD
sbit PLVD
Definition: STC8Gx_REG.h:218
P7M1_ADDRESS
#define P7M1_ADDRESS
Definition: STC8Gx_REG.h:277
SCON
sfr SCON
Definition: STC8Gx_REG.h:658
P61
sbit P61
Definition: STC8Gx_REG.h:400
CH_ADDRESS
#define CH_ADDRESS
Definition: STC8Gx_REG.h:788
P2M1_ADDRESS
#define P2M1_ADDRESS
Definition: STC8Gx_REG.h:272
PWMCFG01
sfr PWMCFG01
Definition: STC8Gx_REG.h:1387
EA
sbit EA
Definition: STC8Gx_REG.h:208
IRTRIM
sfr IRTRIM
Definition: STC8Gx_REG.h:140
P0_ADDRESS
#define P0_ADDRESS
Definition: STC8Gx_REG.h:260
SADDR_ADDRESS
#define SADDR_ADDRESS
Definition: STC8Gx_REG.h:623
DPH1
sfr DPH1
Definition: STC8Gx_REG.h:63
CCON_ADDRESS
#define CCON_ADDRESS
Definition: STC8Gx_REG.h:785
PCON_ADDRESS
#define PCON_ADDRESS
Definition: STC8Gx_REG.h:151
IP3
sfr IP3
Definition: STC8Gx_REG.h:203
P3
sfr P3
Definition: STC8Gx_REG.h:340
CMOD
sfr CMOD
Definition: STC8Gx_REG.h:835
T2H
sfr T2H
Definition: STC8Gx_REG.h:580
P6M0
sfr P6M0
Definition: STC8Gx_REG.h:434
SM2
sbit SM2
Definition: STC8Gx_REG.h:671
P
sbit P
Definition: STC8Gx_REG.h:56
CCAPM1_ADDRESS
#define CCAPM1_ADDRESS
Definition: STC8Gx_REG.h:790
P17
sbit P17
Definition: STC8Gx_REG.h:364
T2L_ADDRESS
#define T2L_ADDRESS
Definition: STC8Gx_REG.h:527
T2H_ADDRESS
#define T2H_ADDRESS
Definition: STC8Gx_REG.h:526
IAP_CMD
sfr IAP_CMD
Definition: STC8Gx_REG.h:768
IAP_TRIG
sfr IAP_TRIG
Definition: STC8Gx_REG.h:769
SADEN
sfr SADEN
Definition: STC8Gx_REG.h:667
P56
sbit P56
Definition: STC8Gx_REG.h:396
CCF3
sbit CCF3
Definition: STC8Gx_REG.h:854
P22
sbit P22
Definition: STC8Gx_REG.h:368
S3BUF
sfr S3BUF
Definition: STC8Gx_REG.h:663
P03
sbit P03
Definition: STC8Gx_REG.h:350
CR
sbit CR
Definition: STC8Gx_REG.h:853
P30
sbit P30
Definition: STC8Gx_REG.h:375
PWMCFG23_ADDRESS
#define PWMCFG23_ADDRESS
Definition: STC8Gx_REG.h:866
T0H
sfr T0H
Definition: STC8Gx_REG.h:569
CCAP2L_ADDRESS
#define CCAP2L_ADDRESS
Definition: STC8Gx_REG.h:794
EX0
sbit EX0
Definition: STC8Gx_REG.h:215
S4CON_ADDRESS
#define S4CON_ADDRESS
Definition: STC8Gx_REG.h:621
P57
sbit P57
Definition: STC8Gx_REG.h:397
IAP_ADDRL_ADDRESS
#define IAP_ADDRL_ADDRESS
Definition: STC8Gx_REG.h:739
IP3H_ADDRESS
#define IP3H_ADDRESS
Definition: STC8Gx_REG.h:170
ISP_ADDRL
sfr ISP_ADDRL
Definition: STC8Gx_REG.h:775
AUXR2
sfr AUXR2
Definition: STC8Gx_REG.h:77
MDU16_TypeDef
Definition: STC8Cx_REG.h:931
SYSCLK_TypeDef
Definition: STC15x_REG.h:78