_s_t_c8_fx___r_e_g_8h_source.html

 /*-----------------------------------------------------------------------

 |                            FILE DESCRIPTION                           |

 -----------------------------------------------------------------------*/

 /*-----------------------------------------------------------------------

   - File name      : STC8Fx_REG.h

   - Author         : Quark Team

   - Update date    : 2020-12-20

   - Copyright      : Gevico Electronic studio

   - Module comments: Header file of STC8Ax MCU model.

 -----------------------------------------------------------------------*/

 /*------------------------------------------------------------------------

 |                            COPYRIGHT NOTICE                            |

 ------------------------------------------------------------------------*/

 /*

  * Copyright (C) 2021, zeweni (17870070675@163.com)


  * This file is part of 8051 ELL low-layer libraries.


  * 8051 ELL low-layer libraries is free software: you can redistribute

  * it and/or modify it under the terms of the Apache-2.0 License.


  * 8051 ELL low-layer libraries is distributed in the hope that it will

  * be useful,but WITHOUT ANY WARRANTY; without even the implied warranty

  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the

  * Apache-2.0 License License for more details.


  * You should have received a copy of the Apache-2.0 License.8051 ELL

  * low-layer libraries. If not, see <http://www.apache.org/licenses/>.

 **/

 /*-----------------------------------------------------------------------

 |                               INCLUDES                                |

 -----------------------------------------------------------------------*/

 #ifndef __STC8Fx_REG_H_

 #define __STC8Fx_REG_H_


 #include "ELL_TYPE.h"


 /*-----------------------------------------------------------------------

 |                                REGISTER                               |

 -----------------------------------------------------------------------*/


 /*--------------------------------------------------------

 | @Description: kernel management                        |

 --------------------------------------------------------*/


 //内核特殊功能寄存器

 sfr ACC         =   0xe0;

 sfr B           =   0xf0;

 sfr PSW         =   0xd0;

 sbit CY         =   PSW^7;

 sbit AC         =   PSW^6;

 sbit F0         =   PSW^5;

 sbit RS1        =   PSW^4;

 sbit RS0        =   PSW^3;

 sbit OV         =   PSW^2;

 sbit F1         =   PSW^1;

 sbit P          =   PSW^0;

 sfr SP          =   0x81;

 sfr DPL         =   0x82;

 sfr DPH         =   0x83;

 sfr TA          =   0xae;

 sfr DPS         =   0xe3;

 sfr DPL1        =   0xe4;

 sfr DPH1        =   0xe5;

 /*--------------------------------------------------------

 | @Description: system management                        |

 --------------------------------------------------------*/


 /* Base address define */

 #define AUXR_ADDRESS       0x8EU

 #define AUXR2_ADDRESS      0x97U

 #define PER_SW1_ADDRESS    0xA2U

 #define PER_SW2_ADDRESS    0xBAU


 /* register */

 sfr AUXR  =          AUXR_ADDRESS;

 sfr AUXR2 =         AUXR2_ADDRESS;

 sfr P_SW1 =       PER_SW1_ADDRESS;

 sfr P_SW2 =       PER_SW2_ADDRESS;


 #define EAXFR_ENABLE()  P_SW2 |= 0x80

 #define EAXFR_DISABLE() P_SW2 &= 0x7F


 /*--------------------------------------------------------

 | @Description: System clock IO register structure       |

 --------------------------------------------------------*/


 typedef struct

 {

     __IO uint8_t CKSEL_REG   ; /*----Clock selection  */


     __IO uint8_t CLKDIV_REG  ; /*----Clock frequency division */


     __IO uint8_t IRC24MCR_REG  ; /*----High internal 24MHz oscillator control */


     __IO uint8_t XOSCCR_REG  ; /*----External oscillator control */


     __IO uint8_t IRC32KCR_REG; /*----Internal 32KHz oscillator control */


 } SYSCLK_TypeDef;


 /*--------------------------------------------------------

 | @Description: System clock peripherals                 |

 --------------------------------------------------------*/


 #define IRTRIM_ADDRESS    0x9FU

 #define LIRTRIM_ADDRESS   0x9EU


 /* System clock base address in the

 internal expansion RAM area */

 #define    SYSCLK_BASE    0xFE00U


 #define    CKSEL_ADDRESS      (SYSCLK_BASE + 0x0000U)

 #define    CLKDIV_ADDRESS     (SYSCLK_BASE + 0x0001U)

 #define    IRC24MCR_ADDRESS   (SYSCLK_BASE + 0x0002U)

 #define    XOSCCR_ADDRESS     (SYSCLK_BASE + 0x0003U)

 #define    IRC32KCR_ADDRESS   (SYSCLK_BASE + 0x0004U)


 /* Define type of SYSCLK */


 #define    SYSCLK     (* (SYSCLK_TypeDef  xdata *) SYSCLK_BASE)


 /* SYSCLIL register */


 #define    CKSEL       ( *(__IO uint8_t xdata *)   CKSEL_ADDRESS)

 #define    CLKDIV      ( *(__IO uint8_t xdata *)  CLKDIV_ADDRESS)

 #define    IRC24MCR    ( *(__IO uint8_t xdata *)  HIRCCR_ADDRESS)

 #define    XOSCCR      ( *(__IO uint8_t xdata *)  XOSCCR_ADDRESS)

 #define    IRC32KCR    ( *(__IO uint8_t xdata *)IRC32KCR_ADDRESS)


 /* IRC frequency adjustment register */


 sfr IRTRIM      =   IRTRIM_ADDRESS;

 sfr LIRTRIM     =   LIRTRIM_ADDRESS;


 #define IRC_24M (*(__I uint8_t idata *)0xFB)


 /*--------------------------------------------------------

 | @Description: Power peripherals                        |

 --------------------------------------------------------*/


 /* Power base address */

 #define    PCON_ADDRESS      0x87U

 #define    VOCTRL_ADDRESS    0xBBU


 /* Power register */

 sfr PCON = PCON_ADDRESS;

 sfr VOCTRL = VOCTRL_ADDRESS;


 /*--------------------------------------------------------

 | @Description: ISR peripherals                          |

 --------------------------------------------------------*/


 /* ISR base address */

 #define    IE_ADDRESS          0xA8U

 #define    IE2_ADDRESS         0xAFU

 #define    IP_ADDRESS          0xB8U

 #define    IP2_ADDRESS         0xB5U

 #define    IPH_ADDRESS         0xB7U

 #define    IP2H_ADDRESS        0xB6U

 #define    INTCLKO_ADDRESS     0x8FU

 #define    AUXINTIF_ADDRESS    0xEFU


 /* IE2 */

 #define ET4         0x40

 #define ET3         0x20

 #define ES4         0x10

 #define ES3         0x08

 #define ET2         0x04

 #define ESPI        0x02

 #define ES2         0x01


 /* IP2 */

 #define PI2C        0x40

 #define PCMP        0x20

 #define PX4         0x10

 #define PPWMFD      0x08

 #define PPWM        0x04

 #define PSPI        0x02

 #define PS2         0x01


 /* IPH */

 #define PPCAH       0x80

 #define PLVDH       0x40

 #define PADCH       0x20

 #define PSH         0x10

 #define PT1H        0x08

 #define PX1H        0x04

 #define PT0H        0x02

 #define PX0H        0x01


 /* IP2H */

 #define PI2CH       0x40

 #define PCMPH       0x20

 #define PX4H        0x10

 #define PPWMFDH     0x08

 #define PPWMH       0x04

 #define PSPIH       0x02

 #define PS2H        0x01


 /* INTCLKO */

 #define EX4         0x40

 #define EX3         0x20

 #define EX2         0x10

 #define T2CLKO      0x04

 #define T1CLKO      0x02

 #define T0CLKO      0x01


 /* AUXINTIF */

 #define INT4IF      0x40

 #define INT3IF      0x20

 #define INT2IF      0x10

 #define T4IF        0x04

 #define T3IF        0x02

 #define T2IF        0x01


 /* ISR register */

 sfr IE   =   IE_ADDRESS;

 sfr IE2  =  IE2_ADDRESS;

 sfr IP   =   IP_ADDRESS;

 sfr IP2  = IP2H_ADDRESS;

 sfr IPH  =  IPH_ADDRESS;

 sfr IP2H = IP2H_ADDRESS;

 sfr INTCLKO  =  INTCLKO_ADDRESS;

 sfr AUXINTIF = AUXINTIF_ADDRESS;


 sbit EA   = IE^7;

 sbit ELVD = IE^6;

 sbit EADC = IE^5;

 sbit ES   = IE^4;

 sbit ET1  = IE^3;

 sbit EX1  = IE^2;

 sbit ET0  = IE^1;

 sbit EX0  = IE^0;


 sbit PPCA = IP^7;

 sbit PLVD = IP^6;

 sbit PADC = IP^5;

 sbit PS   = IP^4;

 sbit PT1  = IP^3;

 sbit PX1  = IP^2;

 sbit PT0  = IP^1;

 sbit PX0  = IP^0;


 /*--------------------------------------------------------

 | @Description: GPIO peripherals                         |

 --------------------------------------------------------*/


 /* Base address define */

 #define    GPIO_BASE       0x80U

 #define    PxM1_BASE       0x93U

 #define    PxM0_BASE       0x94U

 #define BUS_SPEED_ADDRESS  0xA1U


 /* There are internal extended

 ram areas below */

 #define    PxPU_BASE     0xFE10U

 #define    PxNCS_BASE    0xFE18U

 #define    PxSR_BASE     0xFE20U

 #define    PxDR_BASE     0xFE28U

 #define    PxIE_BASE     0xFE30U


 /* GPIO address define */

 #define    P0_ADDRESS  GPIO_BASE

 #define    P1_ADDRESS      0x90U

 #define    P2_ADDRESS      0xA0U

 #define    P3_ADDRESS      0xB0U

 #define    P4_ADDRESS      0xC0U

 #define    P5_ADDRESS      0xC8U

 #define    P6_ADDRESS      0xE8U

 #define    P7_ADDRESS      0xF8U


 /*PxMx address define*/

 #define    P0M1_ADDRESS  PxM1_BASE

 #define    P1M1_ADDRESS      0x91U

 #define    P2M1_ADDRESS      0x95U

 #define    P3M1_ADDRESS      0xB1U

 #define    P4M1_ADDRESS      0xB3U

 #define    P5M1_ADDRESS      0xC9U

 #define    P6M1_ADDRESS      0xCBU

 #define    P7M1_ADDRESS      0xE1U


 #define    P0M0_ADDRESS  PxM0_BASE

 #define    P1M0_ADDRESS      0x92U

 #define    P2M0_ADDRESS      0x96U

 #define    P3M0_ADDRESS      0xB2U

 #define    P4M0_ADDRESS      0xB4U

 #define    P5M0_ADDRESS      0xCAU

 #define    P6M0_ADDRESS      0xCCU

 #define    P7M0_ADDRESS      0xE2U


 /*GPIO pull up address */

 #define    P0PU_ADDRESS    (PxPU_BASE + 0x00U)

 #define    P1PU_ADDRESS    (PxPU_BASE + 0x01U)

 #define    P2PU_ADDRESS    (PxPU_BASE + 0x02U)

 #define    P3PU_ADDRESS    (PxPU_BASE + 0x03U)

 #define    P4PU_ADDRESS    (PxPU_BASE + 0x04U)

 #define    P5PU_ADDRESS    (PxPU_BASE + 0x05U)

 #define    P6PU_ADDRESS    (PxPU_BASE + 0x06U)

 #define    P7PU_ADDRESS    (PxPU_BASE + 0x07U)


 /*GPIO schmidt trigger address */


 #define    P0NCS_ADDRESS   (PxNCS_BASE + 0x00U)

 #define    P1NCS_ADDRESS   (PxNCS_BASE + 0x01U)

 #define    P2NCS_ADDRESS   (PxNCS_BASE + 0x02U)

 #define    P3NCS_ADDRESS   (PxNCS_BASE + 0x03U)

 #define    P4NCS_ADDRESS   (PxNCS_BASE + 0x04U)

 #define    P5NCS_ADDRESS   (PxNCS_BASE + 0x05U)

 #define    P6NCS_ADDRESS   (PxNCS_BASE + 0x06U)

 #define    P7NCS_ADDRESS   (PxNCS_BASE + 0x07U)


 /* GPIO level conversion address */


 #define    P0SR_ADDRESS    (PxSR_BASE + 0x00U)

 #define    P1SR_ADDRESS    (PxSR_BASE + 0x01U)

 #define    P2SR_ADDRESS    (PxSR_BASE + 0x02U)

 #define    P3SR_ADDRESS    (PxSR_BASE + 0x03U)

 #define    P4SR_ADDRESS    (PxSR_BASE + 0x04U)

 #define    P5SR_ADDRESS    (PxSR_BASE + 0x05U)

 #define    P6SR_ADDRESS    (PxSR_BASE + 0x06U)

 #define    P7SR_ADDRESS    (PxSR_BASE + 0x07U)


 /* GPIO drive current address */


 #define    P0DR_ADDRESS    (PxDR_BASE + 0x00U)

 #define    P1DR_ADDRESS    (PxDR_BASE + 0x01U)

 #define    P2DR_ADDRESS    (PxDR_BASE + 0x02U)

 #define    P3DR_ADDRESS    (PxDR_BASE + 0x03U)

 #define    P4DR_ADDRESS    (PxDR_BASE + 0x04U)

 #define    P5DR_ADDRESS    (PxDR_BASE + 0x05U)

 #define    P6DR_ADDRESS    (PxDR_BASE + 0x06U)

 #define    P7DR_ADDRESS    (PxDR_BASE + 0x07U)


 /* GPIO intput enable address*/

 #define    P0IE_ADDRESS    (PxIE_BASE + 0x00U)

 #define    P1IE_ADDRESS    (PxIE_BASE + 0x01U)

 #define    P3IE_ADDRESS    (PxIE_BASE + 0x03U)


 /* GPIO register */

 sfr P0 = P0_ADDRESS;

 sfr P1 = P1_ADDRESS;

 sfr P2 = P2_ADDRESS;

 sfr P3 = P3_ADDRESS;

 sfr P4 = P4_ADDRESS;

 sfr P5 = P5_ADDRESS;

 sfr P6 = P6_ADDRESS;

 sfr P7 = P7_ADDRESS;


 /* GPIO register */

 sbit P00 = P0^0;

 sbit P01 = P0^1;

 sbit P02 = P0^2;

 sbit P03 = P0^3;

 sbit P04 = P0^4;

 sbit P05 = P0^5;

 sbit P06 = P0^6;

 sbit P07 = P0^7;


 /* Pin register */

 sbit P10 = P1^0;

 sbit P11 = P1^1;

 sbit P12 = P1^2;

 sbit P13 = P1^3;

 sbit P14 = P1^4;

 sbit P15 = P1^5;

 sbit P16 = P1^6;

 sbit P17 = P1^7;


 sbit P20 = P2^0;

 sbit P21 = P2^1;

 sbit P22 = P2^2;

 sbit P23 = P2^3;

 sbit P24 = P2^4;

 sbit P25 = P2^5;

 sbit P26 = P2^6;

 sbit P27 = P2^7;


 sbit P30 = P3^0;

 sbit P31 = P3^1;

 sbit P32 = P3^2;

 sbit P33 = P3^3;

 sbit P34 = P3^4;

 sbit P35 = P3^5;

 sbit P36 = P3^6;

 sbit P37 = P3^7;


 sbit P40 = P4^0;

 sbit P41 = P4^1;

 sbit P42 = P4^2;

 sbit P43 = P4^3;

 sbit P44 = P4^4;


 sbit P50 = P5^0;

 sbit P51 = P5^1;

 sbit P52 = P5^2;

 sbit P53 = P5^3;

 sbit P54 = P5^4;

 sbit P55 = P5^5;

 sbit P56 = P5^6;

 sbit P57 = P5^7;


 sbit P60 = P6^0;

 sbit P61 = P6^1;

 sbit P62 = P6^2;

 sbit P63 = P6^3;

 sbit P64 = P6^4;

 sbit P65 = P6^5;

 sbit P66 = P6^6;

 sbit P67 = P6^7;


 sbit P70 = P7^0;

 sbit P71 = P7^1;

 sbit P72 = P7^2;

 sbit P73 = P7^3;

 sbit P74 = P7^4;

 sbit P75 = P7^5;

 sbit P76 = P7^6;

 sbit P77 = P7^7;


 /* GPIO mode register  */

 sfr P0M1 = P0M1_ADDRESS;

 sfr P1M1 = P1M1_ADDRESS;

 sfr P2M1 = P2M1_ADDRESS;

 sfr P3M1 = P3M1_ADDRESS;

 sfr P4M1 = P4M1_ADDRESS;

 sfr P5M1 = P5M1_ADDRESS;

 sfr P6M1 = P6M1_ADDRESS;

 sfr P7M1 = P7M1_ADDRESS;


 /* GPIO mode register  */

 sfr P0M0 = P0M0_ADDRESS;

 sfr P1M0 = P1M0_ADDRESS;

 sfr P2M0 = P2M0_ADDRESS;

 sfr P3M0 = P3M0_ADDRESS;

 sfr P4M0 = P4M0_ADDRESS;

 sfr P5M0 = P5M0_ADDRESS;

 sfr P6M0 = P6M0_ADDRESS;

 sfr P7M0 = P7M0_ADDRESS;


 /* Bus speed control register  */

 sfr BUS_SPEED = BUS_SPEED_ADDRESS;


 /* GPIO Driver register */


 #define    P0PU    ( *(__IO uint8_t xdata *) P0PU_ADDRESS)

 #define    P1PU    ( *(__IO uint8_t xdata *) P1PU_ADDRESS)

 #define    P2PU    ( *(__IO uint8_t xdata *) P2PU_ADDRESS)

 #define    P3PU    ( *(__IO uint8_t xdata *) P3PU_ADDRESS)

 #define    P4PU    ( *(__IO uint8_t xdata *) P4PU_ADDRESS)

 #define    P5PU    ( *(__IO uint8_t xdata *) P5PU_ADDRESS)

 #define    P6PU    ( *(__IO uint8_t xdata *) P6PU_ADDRESS)

 #define    P7PU    ( *(__IO uint8_t xdata *) P7PU_ADDRESS)


 #define    P0SR    ( *(__IO uint8_t xdata *) P0SR_ADDRESS)

 #define    P1SR    ( *(__IO uint8_t xdata *) P1SR_ADDRESS)

 #define    P2SR    ( *(__IO uint8_t xdata *) P2SR_ADDRESS)

 #define    P3SR    ( *(__IO uint8_t xdata *) P3SR_ADDRESS)

 #define    P4SR    ( *(__IO uint8_t xdata *) P4SR_ADDRESS)

 #define    P5SR    ( *(__IO uint8_t xdata *) P5SR_ADDRESS)

 #define    P6SR    ( *(__IO uint8_t xdata *) P6SR_ADDRESS)

 #define    P7SR    ( *(__IO uint8_t xdata *) P7SR_ADDRESS)


 #define    P0DR    ( *(__IO uint8_t xdata *) P0DR_ADDRESS)

 #define    P1DR    ( *(__IO uint8_t xdata *) P1DR_ADDRESS)

 #define    P2DR    ( *(__IO uint8_t xdata *) P2DR_ADDRESS)

 #define    P3DR    ( *(__IO uint8_t xdata *) P3DR_ADDRESS)

 #define    P4DR    ( *(__IO uint8_t xdata *) P4DR_ADDRESS)

 #define    P5DR    ( *(__IO uint8_t xdata *) P5DR_ADDRESS)

 #define    P6DR    ( *(__IO uint8_t xdata *) P6DR_ADDRESS)

 #define    P7DR    ( *(__IO uint8_t xdata *) P7DR_ADDRESS)


 #define    P0IE    ( *(__IO uint8_t xdata *) P0IE_ADDRESS)

 #define    P1IE    ( *(__IO uint8_t xdata *) P1IE_ADDRESS)

 #define    P3IE    ( *(__IO uint8_t xdata *) P3IE_ADDRESS)

 //#define  P2IE    ( *(__IO uint8_t xdata *) P2IE_ADDRESS)

 //#define  P4IE    ( *(__IO uint8_t xdata *) P4IE_ADDRESS)

 //#define  P5IE    ( *(__IO uint8_t xdata *) P5IE_ADDRESS)

 //#define  P6IE    ( *(__IO uint8_t xdata *) P6IE_ADDRESS)

 //#define  P7IE    ( *(__IO uint8_t xdata *) P7IE_ADDRESS)


 #define    P0NCS  ( *(__IO uint8_t xdata *) P0NCS_ADDRESS)

 #define    P1NCS  ( *(__IO uint8_t xdata *) P1NCS_ADDRESS)

 #define    P2NCS  ( *(__IO uint8_t xdata *) P2NCS_ADDRESS)

 #define    P3NCS  ( *(__IO uint8_t xdata *) P3NCS_ADDRESS)

 #define    P4NCS  ( *(__IO uint8_t xdata *) P4NCS_ADDRESS)

 #define    P5NCS  ( *(__IO uint8_t xdata *) P5NCS_ADDRESS)

 #define    P6NCS  ( *(__IO uint8_t xdata *) P6NCS_ADDRESS)

 #define    P7NCS  ( *(__IO uint8_t xdata *) P7NCS_ADDRESS)


 #define GPIO_Px(x)  (P##x)

 #define Px_M1(x)    (P##x##M1)  // GPIO_P0M1 GPIO_P0M0

 #define Px_M0(x)    (P##x##M0)  // P0M1 P0M0

 #define Px_PU(x)    (P##x##PU)

 #define Px_SR(x)    (P##x##SR)

 #define Px_DR(x)    (P##x##DR)

 #define Px_IE(x)    (P##x##IE)

 #define Px_NCS(x)   (P##x##NCS)


 /*--------------------------------------------------------

 | @Description: WDT peripherals                          |

 --------------------------------------------------------*/


 /* Base address define */


 #define   WDT_ADDRESS      0xC1U

 #define   RSTCFG_ADDRESS   0xFFU


 /* WDT register */

 sfr   WDT_CONTR = WDT_ADDRESS;

 //sfr IAP_CONTR = IAR_ADDRESS;

 sfr   RSTCFG = RSTCFG_ADDRESS;


 /*--------------------------------------------------------

 | @Description: TIMER peripherals                        |

 --------------------------------------------------------*/


 /* Base address define */

 #define   TCON_ADDRESS    0x88U

 #define   TMOD_ADDRESS    0x89U

 #define   T0L_ADDRESS     0x8AU

 #define   T1L_ADDRESS     0x8BU

 #define   T0H_ADDRESS     0x8CU

 #define   T1H_ADDRESS     0x8DU

 #define   T4T3M_ADDRESS   0xD1U

 #define   T4H_ADDRESS     0xD2U

 #define   T4L_ADDRESS     0xD3U

 #define   T3H_ADDRESS     0xD4U

 #define   T3L_ADDRESS     0xD5U

 #define   T2H_ADDRESS     0xD6U

 #define   T2L_ADDRESS     0xD7U

 #define   WKTCL_ADDRESS   0xAAU

 #define   WKTCH_ADDRESS   0xABU


 /* TMOD */

 #define T1_GATE     0x80

 #define T1_CT       0x40

 #define T1_M1       0x20

 #define T1_M0       0x10

 #define T0_GATE     0x08

 #define T0_CT       0x04

 #define T0_M1       0x02

 #define T0_M0       0x01


 /* T4T3 */

 #define T4R         0x80

 #define T4_CT       0x40

 #define T4x12       0x20

 #define T4CLKO      0x10

 #define T3R         0x08

 #define T3_CT       0x04

 #define T3x12       0x02

 #define T3CLKO      0x01


 /* WKTCH */

 #define WKTEN       0x80


 /* WDT_CONTR */

 #define WDT_FLAG    0x80

 #define EN_WDT      0x20

 #define CLR_WDT     0x10

 #define IDL_WDT     0x08


 /* TIMER register */

 sfr TCON  =  TCON_ADDRESS;

 sfr TMOD  =  TMOD_ADDRESS;

 sfr T0L   =   T0L_ADDRESS;

 sfr T1L   =   T1L_ADDRESS;

 sfr T0H   =   T0H_ADDRESS;

 sfr T1H   =   T1H_ADDRESS;

 sfr TL0   =   T0L_ADDRESS;

 sfr TL1   =   T1L_ADDRESS;

 sfr TH0   =   T0H_ADDRESS;

 sfr TH1   =   T1H_ADDRESS;

 sfr T4T3M = T4T3M_ADDRESS;

 sfr T4H   =   T4H_ADDRESS;

 sfr T4L   =   T4L_ADDRESS;

 sfr T3H   =   T3H_ADDRESS;

 sfr T3L   =   T3L_ADDRESS;

 sfr T2H   =   T2H_ADDRESS;

 sfr T2L   =   T2L_ADDRESS;

 sfr WKTCL = WKTCL_ADDRESS;

 sfr WKTCH = WKTCH_ADDRESS;


 sbit TF1  =  TCON^7;

 sbit TR1  =  TCON^6;

 sbit TF0  =  TCON^5;

 sbit TR0  =  TCON^4;

 sbit IE1  =  TCON^3;

 sbit IE0  =  TCON^1;


 /* Clock frequency address of timer5 */


 #define FWTH    (*(__I uint8_t idata *)0xF8)

 #define FWTL    (*(__I uint8_t idata *)0xF9)


 /*--------------------------------------------------------

 | @Description: EXTI peripherals                         |

 --------------------------------------------------------*/


 /* EXTI register */

 sbit IT0   =   TCON^0;

 sbit IT1   =   TCON^2;


 /*--------------------------------------------------------

 | @Description: UART peripherals                         |

 --------------------------------------------------------*/


 /* Base address define */


 #define    SCON_ADDRESS    0x98U

 #define    SBUF_ADDRESS    0x99U

 #define    S2CON_ADDRESS   0x9AU

 #define    S2BUF_ADDRESS   0x9BU

 #define    S3CON_ADDRESS   0xACU

 #define    S3BUF_ADDRESS   0xADU

 #define    S4CON_ADDRESS   0x84U

 #define    S4BUF_ADDRESS   0x85U

 #define    SADDR_ADDRESS   0xA9U

 #define    SADEN_ADDRESS   0xB9U


 /* S2CON */

 #define S2SM0       0x80

 #define S2ST4       0x40

 #define S2SM2       0x20

 #define S2REN       0x10

 #define S2TB8       0x08

 #define S2RB8       0x04

 #define S2TI        0x02

 #define S2RI        0x01


 /* S3CON */

 #define S3SM0       0x80

 #define S3ST4       0x40

 #define S3SM2       0x20

 #define S3REN       0x10

 #define S3TB8       0x08

 #define S3RB8       0x04

 #define S3TI        0x02

 #define S3RI        0x01


 /* S4CON */

 #define S4SM0       0x80

 #define S4ST4       0x40

 #define S4SM2       0x20

 #define S4REN       0x10

 #define S4TB8       0x08

 #define S4RB8       0x04

 #define S4TI        0x02

 #define S4RI        0x01


 /* UART register */


 sfr SCON  =  SCON_ADDRESS;

 sfr SBUF  =  SBUF_ADDRESS;

 sfr S2CON = S2CON_ADDRESS;

 sfr S2BUF = S2BUF_ADDRESS;

 sfr S3CON = S3CON_ADDRESS;

 sfr S3BUF = S3BUF_ADDRESS;

 sfr S4CON = S4CON_ADDRESS;

 sfr S4BUF = S4BUF_ADDRESS;

 sfr SADDR = SADDR_ADDRESS;

 sfr SADEN = SADEN_ADDRESS;


 sbit SM0  =   SCON^7;

 sbit SM1  =   SCON^6;

 sbit SM2  =   SCON^5;

 sbit REN  =   SCON^4;

 sbit TB8  =   SCON^3;

 sbit RB8  =   SCON^2;

 sbit TI   =   SCON^1;

 sbit RI   =   SCON^0;


 /*--------------------------------------------------------

 | @Description: COMP peripherals                         |

 --------------------------------------------------------*/


 /* Base address define */

 #define    CMPCR1_ADDRESS    0xE6U

 #define    CMPCR2_ADDRESS    0xE7U


 /* CMPCR1 */

 #define CMPEN       0x80

 #define CMPIF       0x40

 #define PIE         0x20

 #define NIE         0x10

 #define PIS         0x08

 #define NIS         0x04

 #define CMPOE       0x02

 #define CMPRES      0x01


 /* CMPAR2 */

 #define INVCMPO     0x80

 #define DISFLT      0x40


 /* COMP register */

 sfr CMPCR1 = CMPCR1_ADDRESS;

 sfr CMPCR2 = CMPCR2_ADDRESS;


 /* Base address define */

 #define    ADC_CONTR_ADDRESS    0xBCU

 #define    ADC_RES_ADDRESS      0xBDU

 #define    ADC_RESH_ADDRESS     0xBDU

 #define    ADC_RESL_ADDRESS     0xBEU

 #define    ADCCFG_ADDRESS       0xDEU

 #define    ADCTIM_ADDRESS     0xFEA8U

 /* ADC_CONTR */

 #define ADC_POWER   0x80

 #define ADC_START   0x40

 #define ADC_FLAG    0x20


 /* ADCCFG */

 #define ADC_RESFMT  0x20


 /* ADC register */

 sfr ADC_CONTR  = ADC_CONTR_ADDRESS;

 sfr ADC_RES    =  ADC_RESH_ADDRESS;

 sfr ADC_RESL   =  ADC_RESL_ADDRESS;

 sfr ADCCFG     =    ADCCFG_ADDRESS;


 #define ADCTIM    (*(__IO uint8_t xdata *)ADCTIM_ADDRESS)


 /*--------------------------------------------------------

 | @Description: EEPROM peripherals                       |

 --------------------------------------------------------*/


 /*  Base address define */

 #define    IAP_DATA_ADDRESS    0xC2U

 #define    IAP_ADDRH_ADDRESS   0xC3U

 #define    IAP_ADDRL_ADDRESS   0xC4U

 #define    IAP_CMD_ADDRESS     0xC5U

 #define    IAP_TRIG_ADDRESS    0xC6U

 #define    IAP_CONTR_ADDRESS   0xC7U


 #define    ISP_DATA_ADDRESS    0xC2U

 #define    ISP_ADDRH_ADDRESS   0xC3U

 #define    ISP_ADDRL_ADDRESS   0xC4U

 #define    ISP_CMD_ADDRESS     0xC5U

 #define    ISP_TRIG_ADDRESS    0xC6U

 #define    ISP_CONTR_ADDRESS   0xC7U


 /* IAP_CMD */

 #define IAP_IDL     0x00

 #define IAP_READ    0x01

 #define IAP_WRITE   0x02

 #define IAP_ERASE   0x03


 /* IAP_CONTR */

 #define IAPEN       0x80

 #define SWBS        0x40

 #define SWRST       0x20

 #define CMD_FAIL    0x10


 /* EEPROM register */

 sfr IAP_DATA    =   IAP_DATA_ADDRESS;

 sfr IAP_ADDRH   =   IAP_ADDRH_ADDRESS;

 sfr IAP_ADDRL   =   IAP_ADDRL_ADDRESS;

 sfr IAP_CMD     =   IAP_CMD_ADDRESS;

 sfr IAP_TRIG    =   IAP_TRIG_ADDRESS;

 sfr IAP_CONTR   =   IAP_CONTR_ADDRESS;


 sfr ISP_DATA    =   ISP_DATA_ADDRESS;

 sfr ISP_ADDRH   =   ISP_ADDRH_ADDRESS;

 sfr ISP_ADDRL   =   ISP_ADDRL_ADDRESS;

 sfr ISP_CMD     =   ISP_CMD_ADDRESS;

 sfr ISP_TRIG    =   ISP_TRIG_ADDRESS;

 sfr ISP_CONTR   =   ISP_CONTR_ADDRESS;


 /*--------------------------------------------------------

 | @Description: SPI peripherals                          |

 --------------------------------------------------------*/


 /* Base address */

 #define    SPSTAT_ADDRESS   0xCDU

 #define    SPCTL_ADDRESS    0xCEU

 #define    SPDAT_ADDRESS    0xCFU


 /* SPSTAT */

 #define SPIF        0x80

 #define WCOL        0x40


 /* SPCTL */

 #define SSIG        0x80

 #define SPEN        0x40

 #define DORD        0x20

 #define MSTR        0x10

 #define CPOL        0x08

 #define CPHA        0x04


 /* SPI register */

 sfr SPSTAT   =  SPSTAT_ADDRESS;

 sfr SPCTL    =   SPCTL_ADDRESS;

 sfr SPDAT    =   SPDAT_ADDRESS;


 /*--------------------------------------------------------

 | @Description: I2C peripherals                          |

 --------------------------------------------------------*/


 /* Base address */

 #define    I2C_BASE         0xFE80U

 #define    I2CCFG_ADDRESS   (I2C_BASE + 0x00U)

 #define    I2CMSCR_ADDRESS  (I2C_BASE + 0x01U)

 #define    I2CMSST_ADDRESS  (I2C_BASE + 0x02U)

 #define    I2CSLCR_ADDRESS  (I2C_BASE + 0x03U)

 #define    I2CSLST_ADDRESS  (I2C_BASE + 0x04U)

 #define    I2CSLADR_ADDRESS (I2C_BASE + 0x05U)

 #define    I2CTXD_ADDRESS   (I2C_BASE + 0x06U)

 #define    I2CRXD_ADDRESS   (I2C_BASE + 0x07U)


 /* I2CCFG */

 #define ENI2C       0x80

 #define MSSL        0x40


 /* I2CMSCR */

 #define EMSI        0x80


 /* I2CMSST */

 #define MSBUSY      0x80

 #define MSIF        0x40

 #define MSACKI      0x02

 #define MSACKO      0x01


 /* I2CSLCR */

 #define ESTAI       0x40

 #define ERXI        0x20

 #define ETXI        0x10

 #define ESTOI       0x08

 #define SLRST       0x01


 /* I2CSLST */

 #define SLBUSY      0x80

 #define STAIF       0x40

 #define RXIF        0x20

 #define TXIF        0x10

 #define STOIF       0x08

 #define TXING       0x04

 #define SLACKI      0x02

 #define SLACKO      0x01


 /* SPI register */


 #define I2CCFG      (*(__IO uint8_t xdata *)  I2CCFG_ADDRESS)

 #define I2CMSCR     (*(__IO uint8_t xdata *) I2CMSCR_ADDRESS)

 #define I2CMSST     (*(__IO uint8_t xdata *) I2CMSST_ADDRESS)

 #define I2CSLCR     (*(__IO uint8_t xdata *) I2CSLCR_ADDRESS)

 #define I2CSLST     (*(__IO uint8_t xdata * )I2CSLST_ADDRESS)

 #define I2CSLADR    (*(__IO uint8_t xdata *)I2CSLADR_ADDRESS)

 #define I2CTXD      (*(__IO uint8_t xdata *)  I2CTXD_ADDRESS)

 #define I2CRXD      (*(__IO uint8_t xdata *)  I2CRXD_ADDRESS)


 #endif

 /*-----------------------------------------------------------------------

 |          END OF FLIE        (C) COPYRIGHT Gevico Electronics          |

 -----------------------------------------------------------------------*/

ELL_TYPE.h

uint8_t
unsigned char uint8_t
Definition: ELL_TYPE.h:72

__IO
#define __IO
Definition: ELL_TYPE.h:106

P4M0
sfr P4M0
Definition: STC8Fx_REG.h:439

P50
sbit P50
Definition: STC8Fx_REG.h:397

P06
sbit P06
Definition: STC8Fx_REG.h:360

P7M0
sfr P7M0
Definition: STC8Fx_REG.h:442

CY
sbit CY
Definition: STC8Fx_REG.h:51

T0L
sfr T0L
Definition: STC8Fx_REG.h:570

PER_SW2_ADDRESS
#define PER_SW2_ADDRESS
Definition: STC8Fx_REG.h:74

F1
sbit F1
Definition: STC8Fx_REG.h:57

P6M1_ADDRESS
#define P6M1_ADDRESS
Definition: STC8Fx_REG.h:283

P76
sbit P76
Definition: STC8Fx_REG.h:421

T4L
sfr T4L
Definition: STC8Fx_REG.h:580

ISP_ADDRH
sfr ISP_ADDRH
Definition: STC8Fx_REG.h:767

DPH
sfr DPH
Definition: STC8Fx_REG.h:61

P1
sfr P1
Definition: STC8Fx_REG.h:345

P36
sbit P36
Definition: STC8Fx_REG.h:388

IAP_TRIG_ADDRESS
#define IAP_TRIG_ADDRESS
Definition: STC8Fx_REG.h:736

CMPCR1_ADDRESS
#define CMPCR1_ADDRESS
Definition: STC8Fx_REG.h:682

AUXR_ADDRESS
#define AUXR_ADDRESS
Definition: STC8Fx_REG.h:71

TL1
sfr TL1
Definition: STC8Fx_REG.h:575

IPH
sfr IPH
Definition: STC8Fx_REG.h:224

P0M0_ADDRESS
#define P0M0_ADDRESS
Definition: STC8Fx_REG.h:286

P0
sfr P0
Definition: STC8Fx_REG.h:344

P70
sbit P70
Definition: STC8Fx_REG.h:415

PADC
sbit PADC
Definition: STC8Fx_REG.h:240

P2_ADDRESS
#define P2_ADDRESS
Definition: STC8Fx_REG.h:269

ACC
sfr ACC
Definition: STC8Fx_REG.h:48

WDT_CONTR
sfr WDT_CONTR
Definition: STC8Fx_REG.h:513

S4BUF_ADDRESS
#define S4BUF_ADDRESS
Definition: STC8Fx_REG.h:621

P5
sfr P5
Definition: STC8Fx_REG.h:349

PX0
sbit PX0
Definition: STC8Fx_REG.h:245

P24
sbit P24
Definition: STC8Fx_REG.h:377

P10
sbit P10
Definition: STC8Fx_REG.h:364

SPCTL
sfr SPCTL
Definition: STC8Fx_REG.h:796

P_SW2
sfr P_SW2
Definition: STC8Fx_REG.h:80

WKTCL
sfr WKTCL
Definition: STC8Fx_REG.h:585

P13
sbit P13
Definition: STC8Fx_REG.h:367

SPDAT
sfr SPDAT
Definition: STC8Fx_REG.h:797

P0M1
sfr P0M1
Definition: STC8Fx_REG.h:425

P40
sbit P40
Definition: STC8Fx_REG.h:391

EX1
sbit EX1
Definition: STC8Fx_REG.h:234

TR0
sbit TR0
Definition: STC8Fx_REG.h:591

P4
sfr P4
Definition: STC8Fx_REG.h:348

P6M0_ADDRESS
#define P6M0_ADDRESS
Definition: STC8Fx_REG.h:292

P66
sbit P66
Definition: STC8Fx_REG.h:412

ISP_DATA
sfr ISP_DATA
Definition: STC8Fx_REG.h:766

IAP_ADDRH_ADDRESS
#define IAP_ADDRH_ADDRESS
Definition: STC8Fx_REG.h:733

T1L_ADDRESS
#define T1L_ADDRESS
Definition: STC8Fx_REG.h:525

CMPCR1
sfr CMPCR1
Definition: STC8Fx_REG.h:700

P77
sbit P77
Definition: STC8Fx_REG.h:422

IAP_CONTR
sfr IAP_CONTR
Definition: STC8Fx_REG.h:764

PT1
sbit PT1
Definition: STC8Fx_REG.h:242

BUS_SPEED
sfr BUS_SPEED
Definition: STC8Fx_REG.h:445

SM0
sbit SM0
Definition: STC8Fx_REG.h:668

DPL1
sfr DPL1
Definition: STC8Fx_REG.h:64

P14
sbit P14
Definition: STC8Fx_REG.h:368

ADCCFG_ADDRESS
#define ADCCFG_ADDRESS
Definition: STC8Fx_REG.h:708

P34
sbit P34
Definition: STC8Fx_REG.h:386

S3CON
sfr S3CON
Definition: STC8Fx_REG.h:661

P51
sbit P51
Definition: STC8Fx_REG.h:398

P31
sbit P31
Definition: STC8Fx_REG.h:383

P67
sbit P67
Definition: STC8Fx_REG.h:413

F0
sbit F0
Definition: STC8Fx_REG.h:53

P33
sbit P33
Definition: STC8Fx_REG.h:385

P73
sbit P73
Definition: STC8Fx_REG.h:418

ADC_RESL_ADDRESS
#define ADC_RESL_ADDRESS
Definition: STC8Fx_REG.h:707

P01
sbit P01
Definition: STC8Fx_REG.h:355

ISP_TRIG
sfr ISP_TRIG
Definition: STC8Fx_REG.h:770

PPCA
sbit PPCA
Definition: STC8Fx_REG.h:238

P60
sbit P60
Definition: STC8Fx_REG.h:406

P44
sbit P44
Definition: STC8Fx_REG.h:395

TCON_ADDRESS
#define TCON_ADDRESS
Definition: STC8Fx_REG.h:522

IT1
sbit IT1
Definition: STC8Fx_REG.h:606

ADC_CONTR_ADDRESS
#define ADC_CONTR_ADDRESS
Definition: STC8Fx_REG.h:704

SP
sfr SP
Definition: STC8Fx_REG.h:59

P00
sbit P00
Definition: STC8Fx_REG.h:354

TR1
sbit TR1
Definition: STC8Fx_REG.h:589

RSTCFG_ADDRESS
#define RSTCFG_ADDRESS
Definition: STC8Fx_REG.h:510

P5M1_ADDRESS
#define P5M1_ADDRESS
Definition: STC8Fx_REG.h:282

T4T3M
sfr T4T3M
Definition: STC8Fx_REG.h:578

CMPCR2
sfr CMPCR2
Definition: STC8Fx_REG.h:701

P41
sbit P41
Definition: STC8Fx_REG.h:392

LIRTRIM_ADDRESS
#define LIRTRIM_ADDRESS
Definition: STC8Fx_REG.h:109

OV
sbit OV
Definition: STC8Fx_REG.h:56

P15
sbit P15
Definition: STC8Fx_REG.h:369

P32
sbit P32
Definition: STC8Fx_REG.h:384

TL0
sfr TL0
Definition: STC8Fx_REG.h:574

P07
sbit P07
Definition: STC8Fx_REG.h:361

S2BUF_ADDRESS
#define S2BUF_ADDRESS
Definition: STC8Fx_REG.h:617

TH1
sfr TH1
Definition: STC8Fx_REG.h:577

IP2H
sfr IP2H
Definition: STC8Fx_REG.h:225

S4CON
sfr S4CON
Definition: STC8Fx_REG.h:663

PER_SW1_ADDRESS
#define PER_SW1_ADDRESS
Definition: STC8Fx_REG.h:73

INTCLKO
sfr INTCLKO
Definition: STC8Fx_REG.h:226

T4H
sfr T4H
Definition: STC8Fx_REG.h:579

ISP_CMD
sfr ISP_CMD
Definition: STC8Fx_REG.h:769

P4M1
sfr P4M1
Definition: STC8Fx_REG.h:429

P0M1_ADDRESS
#define P0M1_ADDRESS
Definition: STC8Fx_REG.h:277

RS1
sbit RS1
Definition: STC8Fx_REG.h:54

T2L
sfr T2L
Definition: STC8Fx_REG.h:584

IAP_CMD_ADDRESS
#define IAP_CMD_ADDRESS
Definition: STC8Fx_REG.h:735

B
sfr B
Definition: STC8Fx_REG.h:49

S2CON_ADDRESS
#define S2CON_ADDRESS
Definition: STC8Fx_REG.h:616

LIRTRIM
sfr LIRTRIM
Definition: STC8Fx_REG.h:136

CMPCR2_ADDRESS
#define CMPCR2_ADDRESS
Definition: STC8Fx_REG.h:683

P72
sbit P72
Definition: STC8Fx_REG.h:417

P6_ADDRESS
#define P6_ADDRESS
Definition: STC8Fx_REG.h:273

T4H_ADDRESS
#define T4H_ADDRESS
Definition: STC8Fx_REG.h:529

IE1
sbit IE1
Definition: STC8Fx_REG.h:592

P2M0
sfr P2M0
Definition: STC8Fx_REG.h:437

P65
sbit P65
Definition: STC8Fx_REG.h:411

P5M0
sfr P5M0
Definition: STC8Fx_REG.h:440

P23
sbit P23
Definition: STC8Fx_REG.h:376

WKTCH_ADDRESS
#define WKTCH_ADDRESS
Definition: STC8Fx_REG.h:536

P3M0
sfr P3M0
Definition: STC8Fx_REG.h:438

IAP_CONTR_ADDRESS
#define IAP_CONTR_ADDRESS
Definition: STC8Fx_REG.h:737

IP2
sfr IP2
Definition: STC8Fx_REG.h:223

IPH_ADDRESS
#define IPH_ADDRESS
Definition: STC8Fx_REG.h:161

P6
sfr P6
Definition: STC8Fx_REG.h:350

T3L_ADDRESS
#define T3L_ADDRESS
Definition: STC8Fx_REG.h:532

ADC_RES
sfr ADC_RES
Definition: STC8Fx_REG.h:721

P20
sbit P20
Definition: STC8Fx_REG.h:373

P6M1
sfr P6M1
Definition: STC8Fx_REG.h:431

SPSTAT
sfr SPSTAT
Definition: STC8Fx_REG.h:795

IE_ADDRESS
#define IE_ADDRESS
Definition: STC8Fx_REG.h:157

IE
sfr IE
Definition: STC8Fx_REG.h:220

BUS_SPEED_ADDRESS
#define BUS_SPEED_ADDRESS
Definition: STC8Fx_REG.h:256

TA
sfr TA
Definition: STC8Fx_REG.h:62

P_SW1
sfr P_SW1
Definition: STC8Fx_REG.h:79

P2
sfr P2
Definition: STC8Fx_REG.h:346

P53
sbit P53
Definition: STC8Fx_REG.h:400

SM1
sbit SM1
Definition: STC8Fx_REG.h:669

P71
sbit P71
Definition: STC8Fx_REG.h:416

ISP_ADDRH_ADDRESS
#define ISP_ADDRH_ADDRESS
Definition: STC8Fx_REG.h:740

PX1
sbit PX1
Definition: STC8Fx_REG.h:243

ET0
sbit ET0
Definition: STC8Fx_REG.h:235

SADEN_ADDRESS
#define SADEN_ADDRESS
Definition: STC8Fx_REG.h:623

IP
sfr IP
Definition: STC8Fx_REG.h:222

ADCCFG
sfr ADCCFG
Definition: STC8Fx_REG.h:723

DPS
sfr DPS
Definition: STC8Fx_REG.h:63

ISP_CONTR_ADDRESS
#define ISP_CONTR_ADDRESS
Definition: STC8Fx_REG.h:744

S3BUF_ADDRESS
#define S3BUF_ADDRESS
Definition: STC8Fx_REG.h:619

P62
sbit P62
Definition: STC8Fx_REG.h:408

T1H_ADDRESS
#define T1H_ADDRESS
Definition: STC8Fx_REG.h:527

ISP_CONTR
sfr ISP_CONTR
Definition: STC8Fx_REG.h:771

P3_ADDRESS
#define P3_ADDRESS
Definition: STC8Fx_REG.h:270

P7M1
sfr P7M1
Definition: STC8Fx_REG.h:432

P37
sbit P37
Definition: STC8Fx_REG.h:389

P42
sbit P42
Definition: STC8Fx_REG.h:393

DPL
sfr DPL
Definition: STC8Fx_REG.h:60

TI
sbit TI
Definition: STC8Fx_REG.h:674

TMOD_ADDRESS
#define TMOD_ADDRESS
Definition: STC8Fx_REG.h:523

IE0
sbit IE0
Definition: STC8Fx_REG.h:593

T3H_ADDRESS
#define T3H_ADDRESS
Definition: STC8Fx_REG.h:531

P27
sbit P27
Definition: STC8Fx_REG.h:380

IE2_ADDRESS
#define IE2_ADDRESS
Definition: STC8Fx_REG.h:158

TF1
sbit TF1
Definition: STC8Fx_REG.h:588

P52
sbit P52
Definition: STC8Fx_REG.h:399

P4_ADDRESS
#define P4_ADDRESS
Definition: STC8Fx_REG.h:271

T4T3M_ADDRESS
#define T4T3M_ADDRESS
Definition: STC8Fx_REG.h:528

IAP_DATA
sfr IAP_DATA
Definition: STC8Fx_REG.h:759

P25
sbit P25
Definition: STC8Fx_REG.h:378

WDT_ADDRESS
#define WDT_ADDRESS
Definition: STC8Fx_REG.h:509

VOCTRL_ADDRESS
#define VOCTRL_ADDRESS
Definition: STC8Fx_REG.h:146

P26
sbit P26
Definition: STC8Fx_REG.h:379

TF0
sbit TF0
Definition: STC8Fx_REG.h:590

P74
sbit P74
Definition: STC8Fx_REG.h:419

ES
sbit ES
Definition: STC8Fx_REG.h:232

PCON
sfr PCON
Definition: STC8Fx_REG.h:149

S2CON
sfr S2CON
Definition: STC8Fx_REG.h:659

ISP_DATA_ADDRESS
#define ISP_DATA_ADDRESS
Definition: STC8Fx_REG.h:739

SCON_ADDRESS
#define SCON_ADDRESS
Definition: STC8Fx_REG.h:614

T3H
sfr T3H
Definition: STC8Fx_REG.h:581

IAP_DATA_ADDRESS
#define IAP_DATA_ADDRESS
Definition: STC8Fx_REG.h:732

P2M0_ADDRESS
#define P2M0_ADDRESS
Definition: STC8Fx_REG.h:288

P2M1
sfr P2M1
Definition: STC8Fx_REG.h:427

ISP_CMD_ADDRESS
#define ISP_CMD_ADDRESS
Definition: STC8Fx_REG.h:742

P43
sbit P43
Definition: STC8Fx_REG.h:394

P05
sbit P05
Definition: STC8Fx_REG.h:359

T4L_ADDRESS
#define T4L_ADDRESS
Definition: STC8Fx_REG.h:530

SADDR
sfr SADDR
Definition: STC8Fx_REG.h:665

P55
sbit P55
Definition: STC8Fx_REG.h:402

P1_ADDRESS
#define P1_ADDRESS
Definition: STC8Fx_REG.h:268

ET1
sbit ET1
Definition: STC8Fx_REG.h:233

AUXR
sfr AUXR
Definition: STC8Fx_REG.h:77

PS
sbit PS
Definition: STC8Fx_REG.h:241

S4BUF
sfr S4BUF
Definition: STC8Fx_REG.h:664

ISP_ADDRL_ADDRESS
#define ISP_ADDRL_ADDRESS
Definition: STC8Fx_REG.h:741

IAP_ADDRL
sfr IAP_ADDRL
Definition: STC8Fx_REG.h:761

EADC
sbit EADC
Definition: STC8Fx_REG.h:231

P5M0_ADDRESS
#define P5M0_ADDRESS
Definition: STC8Fx_REG.h:291

P1M0
sfr P1M0
Definition: STC8Fx_REG.h:436

P12
sbit P12
Definition: STC8Fx_REG.h:366

P75
sbit P75
Definition: STC8Fx_REG.h:420

P16
sbit P16
Definition: STC8Fx_REG.h:370

PT0
sbit PT0
Definition: STC8Fx_REG.h:244

AUXINTIF
sfr AUXINTIF
Definition: STC8Fx_REG.h:227

P02
sbit P02
Definition: STC8Fx_REG.h:356

IT0
sbit IT0
Definition: STC8Fx_REG.h:605

P5M1
sfr P5M1
Definition: STC8Fx_REG.h:430

P4M0_ADDRESS
#define P4M0_ADDRESS
Definition: STC8Fx_REG.h:290

RB8
sbit RB8
Definition: STC8Fx_REG.h:673

P64
sbit P64
Definition: STC8Fx_REG.h:410

P3M1
sfr P3M1
Definition: STC8Fx_REG.h:428

S2BUF
sfr S2BUF
Definition: STC8Fx_REG.h:660

WKTCL_ADDRESS
#define WKTCL_ADDRESS
Definition: STC8Fx_REG.h:535

S3CON_ADDRESS
#define S3CON_ADDRESS
Definition: STC8Fx_REG.h:618

RSTCFG
sfr RSTCFG
Definition: STC8Fx_REG.h:515

P1M1
sfr P1M1
Definition: STC8Fx_REG.h:426

ELVD
sbit ELVD
Definition: STC8Fx_REG.h:230

T0H_ADDRESS
#define T0H_ADDRESS
Definition: STC8Fx_REG.h:526

ADC_CONTR
sfr ADC_CONTR
Definition: STC8Fx_REG.h:720

ADC_RESH_ADDRESS
#define ADC_RESH_ADDRESS
Definition: STC8Fx_REG.h:706

IAP_ADDRH
sfr IAP_ADDRH
Definition: STC8Fx_REG.h:760

IP2H_ADDRESS
#define IP2H_ADDRESS
Definition: STC8Fx_REG.h:162

ISP_TRIG_ADDRESS
#define ISP_TRIG_ADDRESS
Definition: STC8Fx_REG.h:743

P1M1_ADDRESS
#define P1M1_ADDRESS
Definition: STC8Fx_REG.h:278

TMOD
sfr TMOD
Definition: STC8Fx_REG.h:569

T3L
sfr T3L
Definition: STC8Fx_REG.h:582

P11
sbit P11
Definition: STC8Fx_REG.h:365

TB8
sbit TB8
Definition: STC8Fx_REG.h:672

P4M1_ADDRESS
#define P4M1_ADDRESS
Definition: STC8Fx_REG.h:281

P63
sbit P63
Definition: STC8Fx_REG.h:409

PSW
sfr PSW
Definition: STC8Fx_REG.h:50

INTCLKO_ADDRESS
#define INTCLKO_ADDRESS
Definition: STC8Fx_REG.h:163

AUXINTIF_ADDRESS
#define AUXINTIF_ADDRESS
Definition: STC8Fx_REG.h:164

IE2
sfr IE2
Definition: STC8Fx_REG.h:221

T0L_ADDRESS
#define T0L_ADDRESS
Definition: STC8Fx_REG.h:524

SBUF
sfr SBUF
Definition: STC8Fx_REG.h:658

ADC_RESL
sfr ADC_RESL
Definition: STC8Fx_REG.h:722

P7M0_ADDRESS
#define P7M0_ADDRESS
Definition: STC8Fx_REG.h:293

IRTRIM_ADDRESS
#define IRTRIM_ADDRESS
Definition: STC8Fx_REG.h:108

SPCTL_ADDRESS
#define SPCTL_ADDRESS
Definition: STC8Fx_REG.h:779

VOCTRL
sfr VOCTRL
Definition: STC8Fx_REG.h:150

RS0
sbit RS0
Definition: STC8Fx_REG.h:55

T1L
sfr T1L
Definition: STC8Fx_REG.h:571

TH0
sfr TH0
Definition: STC8Fx_REG.h:576

AUXR2_ADDRESS
#define AUXR2_ADDRESS
Definition: STC8Fx_REG.h:72

RI
sbit RI
Definition: STC8Fx_REG.h:675

P0M0
sfr P0M0
Definition: STC8Fx_REG.h:435

P04
sbit P04
Definition: STC8Fx_REG.h:358

TCON
sfr TCON
Definition: STC8Fx_REG.h:568

AC
sbit AC
Definition: STC8Fx_REG.h:52

P54
sbit P54
Definition: STC8Fx_REG.h:401

REN
sbit REN
Definition: STC8Fx_REG.h:671

P35
sbit P35
Definition: STC8Fx_REG.h:387

P3M1_ADDRESS
#define P3M1_ADDRESS
Definition: STC8Fx_REG.h:280

P1M0_ADDRESS
#define P1M0_ADDRESS
Definition: STC8Fx_REG.h:287

T1H
sfr T1H
Definition: STC8Fx_REG.h:573

P7_ADDRESS
#define P7_ADDRESS
Definition: STC8Fx_REG.h:274

SPSTAT_ADDRESS
#define SPSTAT_ADDRESS
Definition: STC8Fx_REG.h:778

P3M0_ADDRESS
#define P3M0_ADDRESS
Definition: STC8Fx_REG.h:289

IP_ADDRESS
#define IP_ADDRESS
Definition: STC8Fx_REG.h:159

SBUF_ADDRESS
#define SBUF_ADDRESS
Definition: STC8Fx_REG.h:615

WKTCH
sfr WKTCH
Definition: STC8Fx_REG.h:586

P7
sfr P7
Definition: STC8Fx_REG.h:351

P5_ADDRESS
#define P5_ADDRESS
Definition: STC8Fx_REG.h:272

P21
sbit P21
Definition: STC8Fx_REG.h:374

SPDAT_ADDRESS
#define SPDAT_ADDRESS
Definition: STC8Fx_REG.h:780

PLVD
sbit PLVD
Definition: STC8Fx_REG.h:239

P7M1_ADDRESS
#define P7M1_ADDRESS
Definition: STC8Fx_REG.h:284

SCON
sfr SCON
Definition: STC8Fx_REG.h:657

P61
sbit P61
Definition: STC8Fx_REG.h:407

P2M1_ADDRESS
#define P2M1_ADDRESS
Definition: STC8Fx_REG.h:279

EA
sbit EA
Definition: STC8Fx_REG.h:229

IRTRIM
sfr IRTRIM
Definition: STC8Fx_REG.h:135

P0_ADDRESS
#define P0_ADDRESS
Definition: STC8Fx_REG.h:267

SADDR_ADDRESS
#define SADDR_ADDRESS
Definition: STC8Fx_REG.h:622

DPH1
sfr DPH1
Definition: STC8Fx_REG.h:65

PCON_ADDRESS
#define PCON_ADDRESS
Definition: STC8Fx_REG.h:145

P3
sfr P3
Definition: STC8Fx_REG.h:347

T2H
sfr T2H
Definition: STC8Fx_REG.h:583

P6M0
sfr P6M0
Definition: STC8Fx_REG.h:441

SM2
sbit SM2
Definition: STC8Fx_REG.h:670

P
sbit P
Definition: STC8Fx_REG.h:58

P17
sbit P17
Definition: STC8Fx_REG.h:371

T2L_ADDRESS
#define T2L_ADDRESS
Definition: STC8Fx_REG.h:534

T2H_ADDRESS
#define T2H_ADDRESS
Definition: STC8Fx_REG.h:533

IAP_CMD
sfr IAP_CMD
Definition: STC8Fx_REG.h:762

IAP_TRIG
sfr IAP_TRIG
Definition: STC8Fx_REG.h:763

SADEN
sfr SADEN
Definition: STC8Fx_REG.h:666

P56
sbit P56
Definition: STC8Fx_REG.h:403

P22
sbit P22
Definition: STC8Fx_REG.h:375

S3BUF
sfr S3BUF
Definition: STC8Fx_REG.h:662

P03
sbit P03
Definition: STC8Fx_REG.h:357

P30
sbit P30
Definition: STC8Fx_REG.h:382

T0H
sfr T0H
Definition: STC8Fx_REG.h:572

EX0
sbit EX0
Definition: STC8Fx_REG.h:236

S4CON_ADDRESS
#define S4CON_ADDRESS
Definition: STC8Fx_REG.h:620

P57
sbit P57
Definition: STC8Fx_REG.h:404

IAP_ADDRL_ADDRESS
#define IAP_ADDRL_ADDRESS
Definition: STC8Fx_REG.h:734

ISP_ADDRL
sfr ISP_ADDRL
Definition: STC8Fx_REG.h:768

AUXR2
sfr AUXR2
Definition: STC8Fx_REG.h:78

SYSCLK_TypeDef
Definition: STC15x_REG.h:78